1. TEMPLATE DESIGN © 2007 www.PosterPresentations.com Gate-Diffusion Input (GDI) Technique for Low Power CMOS Logic Circuits Design Yerkebulan Saparov, Aktanberdi Zhakupov Abstract Today’s main challenges for most of the VLSI circuit designers are to decrease the area of the circuit and reduce power dissipation. The leading world companies are working on continuous improvement of the existing technologies. Quest for ideas in optimization of productive speed, reducing the propagation delays and power consumption along with compactness and minimization of production costs of triggers are the main objectives of producers of electronics and digital equipment. The question of improvement of logical gate design is particularly acute. Particularly, the power consumption is one of the key factors in any integrated circuit. Considering the complexity of modern integrated circuits, processors now consume large amount of power as they make maximum number of internal transitions. Therefore, the most actual question is to find the techniques to effectively implement low power systems in integrated circuits design. Gate Diffusion input GDI cell manufacturing The main differences of GDI technique lies in the fabrication process of transistors. Regular CMOS cells are fabricated using the method shown in Figure 1, while GDI cells need Twin Tub CMOS Fabrication shown in Figure 2. Basic logic gates design using GDI technique Power consumed, power dissipation There are two main components that constitute the power used by a CMOS integrated circuit: Static power P static = I static V dd Dynamic power P dynamic = P cap + P transient = (C L + C) V dd 2 f N 3 Additional information on GDI using on logic gates Conclusion Reference list Overall, GDI Technique can enrich VLSI designers’ toolbox in the near future. This technique, which is specifically designed for low- power applications, justifies its purpose by showing lowest power dissipation level among CMOS gates. Test chips showed huge improvements in performance, decreased number of transistors and area size over other logic gates. The gate diffusion input is a brand new method for constructing low power digital circuits. It is supposed that Gate Diffusion Input (GDI) Technique is one of emerging options on reduction of production delays of the processor, decrease in power consumption and dissipation along with the simplification of production of integrated micro-schemes. Implementing this method may diminish power losses in the circuit, decreases propagation delay and total area of digital circuits. Basic GDI cell Use for creation of gate considerably reduces number of the used transistors, thus the equipment gives some advantages: Reduction of number of transistors conducts to reduction of losses of power The logical gate designed with equipment can work at low values of VDD Easier manufacturing of logic gates Agarwal, T. 'Step by Step CMOS Fabrication Processing Technology', Buy Electronics & Electrical Projects in India, 2014. [Online]. Available: http://www.edgefx.in/understanding-cmos-fabrication- technology/. [Accessed: 07- Apr- 2015]. Ece.unm.edu, 'CMOS Processing Technology', 2015. [Online]. Available: http://www.ece.unm.edu/~jimp/vlsi/slides/chap3_2.html. [Accessed: 10- Apr- 2015]. Kenia, K. and Kenia, N. 'GDI Technique: A Power- Efficient Method for Digital Circuits', International Journal of Advanced Electrical and Electronics Engineering, vol. 1, no. 3, pp. 87-93, 2012. Kumar, M. A., Selvarani, R. and Kumar, T. Proceedings of International Conference on Advances in Computing. India: Springer, 2013. Morgenshtein, A., Fish, A. and Wagner, I. 'Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits', IEEE Trans. VLSI Syst., vol. 10, no. 5, pp. 566-581, 2002. Morgenshtein, A., Fish A. and Wagner, I. ‘Gate-diffusion Input (GDI) – a Technique for Low Power Design of Digital Circuits: Analysis and Characterization’, Circuits and Systems, vol. 1, no. 1, pp. 477-480, 2002. The use of GDI technique give as opportunity to 1) decrease the Vdd (low-power devices) 2) decrease loses of power due to parasitic capacitance and 3) number of logic transformations (N) OR gate and AND gate with GDI technique (Tanner EDA software) Most of these functions are complex (6–12 transistors) in CMOS, as well as in standard PTL implementations, but very simple (only two transistors per function) in the GDI design method.