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1 Cross ID Tag identification emulator Part A final presentation Performed by: Raanan Steinberg Yido Shalev Project instructor: Yossi Hipsh Technion –

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Presentation on theme: "1 Cross ID Tag identification emulator Part A final presentation Performed by: Raanan Steinberg Yido Shalev Project instructor: Yossi Hipsh Technion –"— Presentation transcript:

1 1 Cross ID Tag identification emulator Part A final presentation Performed by: Raanan Steinberg Yido Shalev Project instructor: Yossi Hipsh Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab

2 2 Overview Electromagnetic tracking and identifying system. Optional applications: –Electromagnetic bar-code –Blind aid devices.

3 3 Overview Transmitter Product Receiver

4 4 Project Goals Design and realization of a digital emulator which Identifies Cross ID tag units. The emulator will operate in base band. Realization will be implemented by high speed digital elements.

5 5 So far… Learning the problem. General design. Equipment learning process Block diagram: –Choosing components. –ID gate realization.

6 6 So far… Manual checking (ID gate)

7 7 `` ID gate test High speed Pulse generator T = 100trise DIP switch Manually controlling delay unit SCOPE trigger

8 8 So far… Controller solution proposals:  FPGA  Microchip controller

9 9 Finally… The chosen one:

10 10 Controller block diagram 8 digital outputs (delay unit control) display LAB-VIEW Controller + Processor Analog input (from the integrator) Digital output (enable for pulse generator)

11 11 `` Block diagram And gate #2 Delay unit Processor + Control unit High speed Pulse generator T = 100 t rise Tags A/D display D 2 = T*G T G E nable E Pulse P Gate Pulse Tag Pulses D1=P*ED1=P*E ∫ D 2 {t 0 + 100T } t0t0 dt Latch Set R Reset S R Int. clock T (Int.) ≈ 10T Main transmitter Tag ID unit LAB-VIEW And gate #1 V out

12 12 System characterization System characterization Pulse Generator Delay unit And gates Integrator Lab-VIEW

13 13 Pulse Generator Pulse generator 33250A 80 MHz Agilent Pulse width 8 ns Rise time 5 ns 2 output (trigger)

14 14 System characterization System characterization Pulse Generator Delay unit And gates Integrator Lab-VIEW

15 15 Monolithic 8bit programmable delay line (3D7408-0.25) Min delay 10-14 ns Max delay 77.75 ns 0.25 ns step Delay unit

16 16 System characterization System characterization Pulse Generator Delay unit And gates Integrator Lab-VIEW

17 17 1 2 3 4 5 6 7 8 MC10EL04 NC D0D0 D1D1 Q Q V CC = (4.2 to 5.7) Volt V EE = 0 Volt And gates MC10EL04 (ON semiconductor)

18 18 System characterization System characterization Pulse Generator Delay unit And gates Integrator Lab-VIEW

19 19 Integrator

20 20 System characterization System characterization Pulse Generator Delay unit And gates Integrator Lab-VIEW

21 21 LAB-VIEW Graphical programming language

22 22 System characterization System characterization Pulse Generator Delay unit And gates Integrator Lab-VIEW

23 23 Coming up Ahead… 1. Programming the controller in Lab- VIEW environment. (7 weeks) 2. Adding the integrator & the and gates to the circuit. (2 weeks) 3. Connecting the controller to the circuit. (2 weeks) 4. Testing the environment. (3 weeks) 5. Final presentation and report.

24 24 Estimated end of project 26/6/05


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