1. Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 12 1 ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Pass Transistor Logic: A Low Power Logic Family Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Fall07/course.html

2. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 122 Low-Power Logic Styles Pass transistor logic Pass transistor logic Dynamic logic Dynamic logic Domino logic Domino logic Adiabatic and charge recovery logic Adiabatic and charge recovery logic Asynchronous logic Asynchronous logic Logic restructuring Logic restructuring

3. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 123 Pass Transistor Logic (PTL) Requires fewer transistors Requires fewer transistors Smaller area Smaller area Reduced capacitance Reduced capacitance Reduced energy and power Reduced energy and power

4. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 124 CMOS AND Gate F = AB A B A B

5. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 125 Pass Transistor AND Gate A B F = AB 0 Need 4 transistors instead of 6 for CMOS AND gate.

6. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 126 CMOS OR Gate F = A + B A B A B

7. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 127 Pass Transistor OR Gate 1 B F = A + B A Need 4 transistors instead of 6 for CMOS OR gate.

8. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 128 Reduced Voltage Swing VDD = 2.5V IN OUT n transistors, W/L = 0.5μ/0.25μ p transistors, W/L = 1.5μ/0.25μ Vx = VDD – V tn

9. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 129 Spice Simulation Time, ns 00.5 1.0 1.5 2.0 3.0 2.0 1.0 0.0 Voltage, V IN OUT Vx J. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital Integrated Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003.

10. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1210 Voltage Transfer Characteristic (VTC) of AND Gate A B F = AB 0 n transistors, W/L = 0.5μ/0.25μ p transistors, W/L = 1.5μ/0.25μ

11. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1211 VTC: Spice Simulation Vin, V 00.5 1.0 1.5 2.0 2.5 3.0 2.0 1.0 0.0 F, V B = VDD A = 0 → VDD A = VDD, B = 0 → VDD A = B = 0 → VDD VDD – V tn

12. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1212 Energy VDD = 2.5V 0 → VDD CL T E 0→1 =∫ P(t) dt = VDD ∫ i(t) dt 0 VDD-V tn = VDD ∫ CL dVout = CL VDD (VDD – V tn ) < CL VDD 2 0 If this voltage is insufficient for turning the pMOS Transistor in inverter off, leakage power will be consumed. Vout i(t)

13. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1213 Energy: PTL vs. CMOS PTL consumes less dynamic power than static CMOS Logic. PTL consumes less dynamic power than static CMOS Logic. PTL leakage may be higher when output is low, because the reduced voltage level may be insufficient to turn the PMOS transistor in the inverter off. PTL leakage may be higher when output is low, because the reduced voltage level may be insufficient to turn the PMOS transistor in the inverter off.

14. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1214 Ways to Reduce Leakage Level restoration Level restoration Multiple-threshold transistors Multiple-threshold transistors Transmission-gate logic Transmission-gate logic

15. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1215 Level Restoration A=1 B=1 CL Vout VDDLevel restorer Level restorer device should be weaker than the nMOS pass transistor. Otherwise, VDD → 0 transition at Vout will be impossible. 0

16. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1216 Multiple-Threshold Transistors Use zero-threshold pass-transistors. Use zero-threshold pass-transistors. Use high-threshold transistors in all other gates. Use high-threshold transistors in all other gates. This can cause leakage through multiple gates. This can cause leakage through multiple gates.

17. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1217 Leakage Through Zero-Threshold Transistors 0 1 1 0 Zero or low-threshold transistors Leakage current path

18. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1218 Transmission-Gate Logic Provides both power and ground levels. Provides both power and ground levels. Good design, except needs more transistors. Good design, except needs more transistors. ASBASB S’A’ + SB’ Inverting multiplexer

19. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1219 Transmission-Gate XOR A AB’+A’B B

20. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1220 A Logic Library Cell Number of transistors CMOSTGL OR026 MUX21126 AND026 XOR2126 AND038 AOI3210 OAI216 OAI3210 AO218 NOR048 OR038 NOR02_2x4 OAI22110 NAND02_2x4 AOI32112 INV022 DFFR34

21. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1221 Synthesis of PTL ABCZ 0000 0010 0100 0111 1000 1011 1101 1111 Shannon’s expansion: Z =AB + BC + AC =A(B+BC+C) + A’(BC) =A(B+C) + A’BC =A[B+B’C] + A’[BC] A 1 0 B CC10 Z

22. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1222 Pass-Transistor Cell

23. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1223 Synthesis of Z = A’B + B’C + A’C’ B 0 A C Z C = 1, Z = A’B + B’ B = 1, Z = A’ B = 0, Z = 1 C = 0, Z = A’

24. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1224 Synthesis of Z = A’ + BC’ + B’C 0 B B’ A A’ C C’ Z A = 1, Z = BC’ + B’C B = 1, Z = C’ B = 0, Z = C A = 0, Z = 1

25. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1225 Synthesis of Z = AB’C’ + A’B’C A’ A B’ B C’ C 1 Z A = 1, Z = B’C’ B = 1, Z = 0 B = 0, Z = C’ A = 0, Z = B’C B = 1, Z = 0 B = 0, Z = C

26. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1226 CPL: Complementary Pass- Transistor Logic Every signal and its complement is generated. Every signal and its complement is generated. Gates are static, because the output is connected to either VDD or GND. Gates are static, because the output is connected to either VDD or GND. Design is modular; same cell can produce various gates by simply permuting the input signals. Design is modular; same cell can produce various gates by simply permuting the input signals. Also called differential pass-transistor logic (DPL) Also called differential pass-transistor logic (DPL)

27. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1227 A CPL Cell

28. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1228 CPL Cell Used As AND/NAND A B A’ B’ B B’ Z = AB Z’ = (AB)’

29. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1229 CPL Cell Used As OR/NOR A B A’ B’ B’ B Z = A + B Z’ = (A + B)’

30. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1230 CPL Cell Used As XOR/XNOR A A’ A’ A B’ B Z = AB’ + A’B Z’ = AB + A’B’

31. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1231 CPL vs. CMOS CPL requires fewer transistors. CPL requires fewer transistors. Useful for modular (array) circuits like adders, multipliers, barrel shifter, etc. Useful for modular (array) circuits like adders, multipliers, barrel shifter, etc. CPL operation can be faster and energy efficient. CPL operation can be faster and energy efficient. Following example is taken from: Following example is taken from: M. E. Elrabaa, I. S. Abu-Khater, and M. I. Elmasry, Advanced Low-Power Digital Circuit Techniques, Springer, 1997, Chapter 2. M. E. Elrabaa, I. S. Abu-Khater, and M. I. Elmasry, Advanced Low-Power Digital Circuit Techniques, Springer, 1997, Chapter 2.

32. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1232 Example: 4-Bit Carry Select Adder A_1 B_1 Adder cell S1’ S0’ C0’ C0 C1’ C1 A_2 B_2 Adder cell S1’ S0’ C0’ C0 C1’ C1 M M M M M M M MM M S_1 C’_0 C_0 S_2 A_3 B_3 Adder cell S1’ S0’ C0’ C0 C1’ C1 A_4 B_4 Adder cell S1’ S0’ C0’ C0 C1’ C1 M M M M M M M MM M S_3 C’_2 S_4 C_4 C’_4

33. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1233 CMOS Carry-Select Adder Cell S1’ S0’ C0’ C0 C1’ C1 Ai Bi

34. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1234 CPL Adder Cell Ai Bi S1’ S0’ C0’ C0 C1’ C1

35. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1235 CPL Multiplexer Cell Ci Ci’ in1 in2 in1 in2 Ci Ci’ M out

36. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1236 32-Bit Adders in 0.8μ, 3.3V Type of design Type of logic Energy μW/MHz Delayns Minimum transistor size CMOS90.011.0 CPL65.010.0 Transistor sizing for delay optimization CMOS93.010.5 CPL72.07.5

37. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1237 References G. R. Cho and T. Chen, “On the Impact of Technology Scaling on Mixed PTL/Static Logic,” Proc. IEEE Int. Conf. Computer Design, 2002. G. R. Cho and T. Chen, “On the Impact of Technology Scaling on Mixed PTL/Static Logic,” Proc. IEEE Int. Conf. Computer Design, 2002. R. Zimmermann and W. Fichtner, “Low- Power Logic Styles: CMOS Versus Pass- Transistor Logic,” IEEE J. Solid State Circuits, vol. 32, no. 7, pp. 1079-1090, July 1997. R. Zimmermann and W. Fichtner, “Low- Power Logic Styles: CMOS Versus Pass- Transistor Logic,” IEEE J. Solid State Circuits, vol. 32, no. 7, pp. 1079-1090, July 1997.