EE 5324 – VLSI Design II Part I: Introduction Kia Bazargan

http://www.ece.umn.edu/users/kia/Courses/EE5324 Kia Bazargan
EE 5324 – VLSI Design II Part I: Introduction Kia Bazargan University of Minnesota Spring 2006 EE VLSI Design II - © Kia Bazargan VLSI Design II – © Kia Bazargan

EE 5324 - VLSI Design II - © Kia Bazargan
Section Outline Administrative Issues Semiconductor industry trends Chip implementation methodologies Design methodologies Outline Spring 2006 EE VLSI Design II - © Kia Bazargan

Administrative Issues
Administrative Issues Class Time and venue:______________________________ Web page: Textbook: J. M. Rabaey, "Digital Integrated Circuits: A Design Perspective", Prentice Hall, 2nd Ed., 2002 CAD software: Cadence / HSpice / Magic? Grades 40% homework and quizzes 25% midterm – open book. Date: ______________ 35% Final exam – open book. Date: ______________ Check out the web page regularly! Handouts will be distributed in class (off-site students can download from the web page) Spring 2006 EE VLSI Design II - © Kia Bazargan VLSI Design II – © Kia Bazargan

Administrative Issues
Personnel Instructor: Kia Bazargan Phone: (612) Office: EE/CSci 4-159 Office hours: __________________________ TA: ______________ ______________________________ Phone: ___________ Office: _____________ Office hours: ___________________ Spring 2006 EE VLSI Design II - © Kia Bazargan

Administrative (cont.)
Policies Homework must be received before class 1min – 24 hours late: 50% of the grade > 24 hours late: 0% Zero tolerance for cheating Collaboration OK, copying NOT OK Include ID on all homework, exams, etc. No extra work for extra credit Check the class web pages regularly, the students are responsible for checking the discussion threads and announcements regularly Spring 2006 EE VLSI Design II - © Kia Bazargan

This is a sample text, not printed, but animated
Online Slides Slides are posted on the web Handouts as .pdf file Powerpoint files provided too NOTE: some slides are animated (like this one) Click on the slide to see the animation Click once more. Note: some slides have notes! (like this one) Some slides contain text that is not printed in the handouts, but animated. These are left for you to fill out in the handouts. An example is shown below (animated: click to see) Slide “notes” can be found here. You might need to scroll to read the entire text. Some slides are animated. Click on each slide before advancing to the next one to see the animation (if any). This is a sample text, not printed, but animated Spring 2006 EE VLSI Design II - © Kia Bazargan VLSI Design II – © Kia Bazargan

References and Copyright
Textbooks (only [Rab02] required) [WE92] N. H. E. Weste, K. Eshraghian “Principles of CMOS VLSI Design: A System Perspective” Addison-Wesley, 2nd Ed., 1992. [Rab02] J. M. Rabaey “Digital Integrated Circuits: A Design Perspective” Prentice Hall, 2nd Ed., 2002. [Par00] B. Parhami “Computer Arithmetic: Algorithms and Hardware Designs” Oxford University Press, 2000. [KL99] S. Kang, Y. Levlebici “CMOS Digital Integrated Circuits: Analysis and Design” McGraw-Hill, 2nd Ed., 1999. Spring 2006 EE VLSI Design II - © Kia Bazargan

References and Copyright (cont.)
Slides used: [©Hauck] © Scott A. Hauck, ; G. Borriello, C. Ebeling, S. Burns, 1995, University of Washington (Modified by Kia when necessary) [©Prentice Hall] © Prentice Hall 1995, © UCB Slides for [Rab96] Spring 2006 EE VLSI Design II - © Kia Bazargan

What is This Course All About?
What is This Course All About? Prerequisite Basic CMOS design Static/dynamic circuit design Layout / Simulation What is different from “VLSI Design I”? Higher-level of design (closer to architecture) Emphasis on performance, processor cores, fault tolerance What is covered? Mostly arithmetic circuits Memories Test and testability New issues and design techniques Combination of algorithmic / structural / gate-level optimization are used Emphasis on performance Spring 2006 EE VLSI Design II - © Kia Bazargan VLSI Design II – © Kia Bazargan

Course Outline CMOS Designs Arithmetic & logic unit (ALU) Bitwise operations Datapath layout Adders Basic adders: carry propagation, Carry Look-ahead, Manchester Carry Chain More complex adders: Carry Save Adder, Brent-Kung Fast adders: Carry-Select adder, Wallace tree Multipliers Shift/Add multiplication Booth encoding Multiplication by constants Floating point multiplication Spring 2006 EE VLSI Design II - © Kia Bazargan VLSI Design II – © Kia Bazargan

Course Outline (cont) CMOS Designs (cont) Shift/Rotate operations Memories Memory cells: static and dynamic Memory arrays: address decoders, sensors and amplifiers Test and testability Fault models Design techniques: scan design, built-in self-test New design techniques/platforms CORDIC algorithms Bit-serial computations [Recent circuit examples] Spring 2006 EE VLSI Design II - © Kia Bazargan

IC Products Processors CPU, DSP, Controllers Memory chips RAM, ROM, EEPROM Analog Mobile communication, audio/video processing Programmable PLA, FPGA Embedded systems Used in cars, factories Network cards System-on-chip (SoC) Digital Signal Processing (DSP) chips are used all over the place: audio, image processing, satellite applications, etc. Memory performance always behind CPU speed, greater need for more capacity, bandwidth Network processors: low-cost, versatile, fast designs needed for the increasing internet applications, protocols, etc. Images: amazon.com Spring 2006 EE VLSI Design II - © Kia Bazargan VLSI Design II – © Kia Bazargan

IC Product Market Shares
Source: Electronic Business Spring 2006 EE VLSI Design II - © Kia Bazargan

Semiconductor Industry Growth Rates
Source: (McClean Report) Spring 2006 EE VLSI Design II - © Kia Bazargan

Source: http://www.edat.com/edac
More Demand for EDA CAE = Computer Aided Engineering Source: Spring 2006 EE VLSI Design II - © Kia Bazargan

Source: http://www.edat.com/edac
Growth in System Size CAGR = Compound Annual Growth Rate Source: Spring 2006 EE VLSI Design II - © Kia Bazargan

Example: Intel Processor Sizes
Silicon Process Technology Intel386TM DX Processor Intel486TM DX Pentium® Processor Pentium® Pro & Pentium® II Processors Source: Spring 2006 EE VLSI Design II - © Kia Bazargan

Implementation Methodologies
Digital Ckt Implementation Approaches Custom Semi custom [© Prentice Hall] Spring 2006 EE VLSI Design II - © Kia Bazargan

Custom Design Using Magic we can get exactly what we want. However: Complex to design Takes weeks to fabricate High design costs High overhead (non-recurring – NRE) costs How do we automate the mapping? [© Hauck] Spring 2006 EE VLSI Design II - © Kia Bazargan VLSI Design II – © Kia Bazargan

Standard Cells Develop predefined implementations of basic gates with standard form-factor [© Hauck] Spring 2006 EE VLSI Design II - © Kia Bazargan

Standard Cells Use regular layout Can automate the mapping process, but Takes weeks to fabricate No economies of scale PWR GND CELL 1 CELL 2 CELL 3 CELL 4 CELL 5 CELL 6 ROUTING Cells PWR GND CELL 7 CELL 8 CELL 9 CELL 10 ROUTING Cells ROUTING Cells ROUTING PWR GND CELL 11 CELL 12 CELL 13 CELL 14 CELL 15 CELL 16 Cells ROUTING [© Hauck] Spring 2006 EE VLSI Design II - © Kia Bazargan

Combined Standard Cell and Full Custom
Use full custom for regular structures & critical paths Standard cells handle complex logic & non-critical logic [© Hauck] Spring 2006 EE VLSI Design II - © Kia Bazargan

Mask-Programmable Gate Array (MPGA)
Prefabricate all but the metal layers [© Hauck] Spring 2006 EE VLSI Design II - © Kia Bazargan

Sea-of-Gates (SOG) Prefabricate all but the metal layers and the contacts [© Hauck] Spring 2006 EE VLSI Design II - © Kia Bazargan

Discrete Components Prefabricate lots of small, simple parts. Wire them together. D Q [© Hauck] Spring 2006 EE VLSI Design II - © Kia Bazargan

Programmable Logic Devices
Categories of prewired arrays (or field-programmable devices): Fuse-based (program-once) Non-volatile EPROM based RAM based Recently: VPGA (Via-Programmable Gate Array) Structured ASIC [© Prentice-Hall] Spring 2006 EE VLSI Design II - © Kia Bazargan

Programmable Logic Devices
PAL PLA PROM [© Prentice-Hall] Spring 2006 EE VLSI Design II - © Kia Bazargan

Fabrication Process Revisited
Speed up fabrication & get economies of scale by prefabricating some layers n-SUBSTRATE (a) field oxide etching n-SUBSTRATE p-WELL (b) p-well diffusion n-SUBSTRATE p-WELL (c) field oxide etching n-SUBSTRATE p-WELL (d) gate oxidation n-SUBSTRATE p-WELL (e) polysilicon definition n-SUBSTRATE p-WELL p+ (f) p-plus diffusion n-SUBSTRATE p-WELL n+ p+ (g) n-plus diffusion n-SUBSTRATE p-WELL n+ p+ (h) oxide growth n-SUBSTRATE p-WELL n+ p+ (i) contact cuts (j) metalization p-WELL n+ p+ n-SUBSTRATE Spring 2006 EE VLSI Design II - © Kia Bazargan [© Hauck]

Programming Technologies
Mask-programmed Antifuse EPROM EEPROM SRAM Polysilicon Field Oxide N+ diffusion ONO Dielectric access gate floating gate n+ source n+ drain P-Type Silicon Write ~Q Q [© Hauck] Spring 2006 EE VLSI Design II - © Kia Bazargan

RAMs, ROMs Given a RAM/ROM with 8k memory locations, in 1k*8bit organization 10 address lines Can implement 8 arbitrary 10-input functions (but inefficiently) ROM A B C D E F G H 000 001 010 011 100 101 110 111 I1 I2 I3 [© Hauck] Spring 2006 EE VLSI Design II - © Kia Bazargan

Field Programmable Gate Arrays (FPGAs)
Logic cells embedded in a general routing structure Logic cells usually contain: 5-input function calculator Flip-flops All features electronically (re)programmable RAM RAM RAM RAM RAM RAM M RAM RAM AM RAM RAM [© Hauck] Spring 2006 EE VLSI Design II - © Kia Bazargan

Multi-Mode Systems Tektronix PhaserCard printer controllers Different configurations for different printers Andromeda Systems disk controller Field upgrades performed by modem Radius pivoting monitor Different configurations for landscape & portrait Honeywell tape drive Different configurations for read & write operations ROM Config1 Config2 Config3 Config4 FPGA [© Hauck] Spring 2006 EE VLSI Design II - © Kia Bazargan

Microprocessors & Microcontrollers
Microcontrollers are simple 1-chip computers optimized for embedded control Cheap, ubiquitous, can handle complex control flow (relatively slowly) Sensor CPU I/O RAM ROM Actuator [© Hauck] Spring 2006 EE VLSI Design II - © Kia Bazargan

Digital Signal Processors (DSPs)
Fast multiply-accumulate for signal filtering, etc. REGISTER MUX PC PROGRAM CONTROLLER MULTIPLIER REGISTER Address REGISTER MUX Address MUX PROGRAM ROM SHIFTER DATA RAM ALU I/O CONTROLLER Program Bus ACCUMULATOR SHIFTER Data Bus [© Hauck] Spring 2006 EE VLSI Design II - © Kia Bazargan

Digital Logic Implementation Alternatives
Full Custom PWR GND CELL 1 CELL 2 CELL 3 CELL 4 CELL 5 CELL 6 CELL 8 CELL 7 CELL 10 CELL 9 Standard Cells Gate Arrays Field-Programmable Gate Arrays (FPGAs) i6 i5 i4 i3 i2 i1 Programmable Logic Devices o1 Discrete Components Spring 2006 EE VLSI Design II - © Kia Bazargan

To Probe Further... D. G. Chinnery and K. Keutzer, “Closing the Gap Between ASIC and Custom: An ASIC Perspective”, Design Automation Conference (DAC), pp , 2000. Spring 2006 EE VLSI Design II - © Kia Bazargan

IC Design Steps (cont.) High-level Description Structural Description
IC Design Steps (cont.) High-level Description Structural Description Specifications Behavioral VHDL, C Structural VHDL These steps are not engraved in stone: there are lots of varieties High-level description defines major components of the design and their interaction Structural description is usually at Register Transfer Level (RTL). RTL description deals with more details, lists signals, block components. Languages such as VHDL are used to describe the architecture. Spring 2006 EE VLSI Design II - © Kia Bazargan Figs. [©Sherwani] VLSI Design II – © Kia Bazargan

IC Design Steps (cont.) Synthesis Physical Design Technology Mapping
IC Design Steps (cont.) High-level Description Structural Description Specifications Logic Description Synthesis Physical Design Technology Mapping Placed & Routed Design Gate-level Design Again, these steps are not engraved in stone: there are lots of varieties Logic description is usually generated by Computer Aided Design (CAD) tools Gate-level design (also known as “netlist”) describes the design in the atomic entities of the technology. For a CMOS design, transistors are used. In an FPGA design, look-up tables (LUTs) are used. The process of converting a logic description to a gate-level design is called technology mapping. There are a *lot* of optimizations involved after technology mapping We might go back and forth between these steps (e.g., after gate-level desc., we might simulate and find bugs => go back to RTL or high-level description and fix the bug) I haven’t shown testing/verification This course helps you understand the methods and algorithms used for high-level optimizations of the design (at algorithmic/architectural level) You will design high performance circuits Fabri- cation X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Packaging Spring 2006 EE VLSI Design II - © Kia Bazargan Figs. [©Sherwani] VLSI Design II – © Kia Bazargan

IC Design Steps (cont.) Synthesis Physical Design Technology Mapping
IC Design Steps (cont.) High-level Description Structural Description Specifications Logic Description Synthesis Physical Design Technology Mapping Placed & Routed Design Gate-level Design The scope of the course is shown in the dotted line. Fabri- cation Packaging Spring 2006 EE VLSI Design II - © Kia Bazargan VLSI Design II – © Kia Bazargan

The Big Picture: IC Design Methods
The Big Picture: IC Design Methods Cost / Development Time Design Methods Quality % Companies involved Full Custom Standard Cell Library Design ASIC – Standard Cell Design What is the difference between full custom and ASIC design? Tools used in Full Custom would be Magic-like, and tools used in RTL-Level Design would be CAD tools for synthesis, PD, etc. Since Full Custom costly (number of designers, design time, fabrication cost, scalability, etc.) only companies like Intel afford This course will be related to the first two (possibly third) design methods. RTL-Level Design Spring 2006 EE VLSI Design II - © Kia Bazargan VLSI Design II – © Kia Bazargan

Optimization: Levels of Abstraction
Algorithmic Encoding data, computation scheduling, balancing delays of components, etc. Gate-level Reduce fan-out, capacitance Gate duplication, buffer insertion Layout Move transistors driven by late inputs closer to the output Effectiveness Level of detail Spring 2006 EE VLSI Design II - © Kia Bazargan

Where Is This Course in the Big Picture?
Where Is This Course in the Big Picture? VLSI related courses: VLSI CAD VLSI Design Others EE 5301 VLSI Design Automation I EE 5302 Automation II EE 5323 VLSI Design I EE 5324 VLSI Design II EE 4301 Digital Design With Programmable Logic EE 5329 VLSI Digital Signal Processing Systems The VLSI CAD courses cover algorithms that are used in CAD tools (used in ASIC designs) The VLSI Design courses deal with the full-custom methodology EE 5333 Analog Integrated Circuit Design EE 5549 Digital Signal Processing Structures for VLSI Spring 2006 EE VLSI Design II - © Kia Bazargan VLSI Design II – © Kia Bazargan

Layouts [© Prentice Hall]
Full Custom Design Component Design Structural/RTL Description Mem Ctrl Comp. Unit Reg File Place & Route A/D PLA I/O comp RAM A team of engineers work on each component of the system After each component is designed / tested / optimized, put together the whole thing Automatic tools might be used in each of the stages ... Floorplan [©Sherwani] Layouts [© Prentice Hall] Spring 2006 EE VLSI Design II - © Kia Bazargan VLSI Design II – © Kia Bazargan

ASIC Design Structural/ RTL Description Mem Ctrl Comp. Unit Reg File HDL Programming P_Inp: process (Reset, Clock) begin if (Reset = '1') then sum <= ( others => '0' ); input_nums_read <= '0'; sum_ready <= '0'; add82 : kadd8 port map ( a => add_i1, b => add_i2, ci => carry, s => sum_o); Mult_i1 <= sum_o(7 downto 0); D C B A Designers describe the hardware in high-level languages such as VHDL and Verilog A lot of automation is used (and the quality of the chip won’t be as good as full-custom – maybe up to 20x worse) The cell library is developed by CAD companies. It contains gates such as AND, OR, XOR, or could even offer more complex cells such as adders and multipliers. C D A B Cell library Floorplan [©Sherwani] Spring 2006 EE VLSI Design II - © Kia Bazargan VLSI Design II – © Kia Bazargan

More Issues to Consider
More Issues to Consider Area/speed trade-off Power consumption a new factor 80 look-ahead select bypass manchester mirror static manchester look-ahead select static mirror bypass 60 0.4 Area (mm2) 40 tp(sec) 0.2 20 Some constraints are not very well known in advance (e.g., you just have an estimate of the area that you can use) Might have to design at RTL/gate level and simulate to find the best candidate Engineering is facing with trade-offs everyday! 10 20 10 20 N N [© Prentice Hall] Spring 2006 EE VLSI Design II - © Kia Bazargan VLSI Design II – © Kia Bazargan

More Issues to Consider (cont.)
More Issues to Consider (cont.) Aspect ratio, area budgets, datapath layout Power and clock grid Wires (M1) Control wires (M1) GND Well Signal wires (M2) V Signal wires (M2) DD Some constraints are globally imposed on the design (decided before the teams start working on the components) You might have to design your modules in a way that horizontal flipping and/or rotation would be possible Figures: [© Prentice Hall] Well GND GND GND V DD Approach I — Approach II — Signal and power lines parallel Signal and power lines perpendicular Spring 2006 EE VLSI Design II - © Kia Bazargan VLSI Design II – © Kia Bazargan

Datapath Layout Example: Adder
Datapath Layout Example: Adder Standard cell layout Bit-slice cell layout Depending on the design model, you might end up with drastically different layouts Again, you should have a “global view” in mind [WE92] p.521 Spring 2006 EE VLSI Design II - © Kia Bazargan VLSI Design II – © Kia Bazargan

Architecture of a CPU Flags: overflow, zero, etc. Control function Read/write Mem Register File Data path This is a very simple CPU The control unit is a state machine. Schedules the operations, synchronized different components Memory could be RAM, ROM, Content-Addressable Memory (CAM) Data path is the manipulator of data. Performs arithmetic and logic operations I haven’t shown I/O Spring 2006 EE VLSI Design II - © Kia Bazargan VLSI Design II – © Kia Bazargan

Arithmetic and Logic Unit (ALU)
Functions Arithmetic (add, sub, inc, dec) Logic (and, or, not, xor) Comparison (<, >, <=, >=, !=) Control signals Function selection Operation mode (signed, unsigned) Output Operation result (data) Flags (overflow, zero, negative) Spring 2006 EE VLSI Design II - © Kia Bazargan

Simple ALU Example Control Register Adder Shifter Multiplexer Bit 3 Bit 2 Data Out Data in Bit 1 Bit 0 The inputs are stored in registers Operations are performed on the inputs Mux selects the functional unit (e.g., adder or shifter) whose output should be connected to “data out” Bit-sliced fashion Adder important: very common, a lot of effort has been put in optimization Data widths: 8, 12, 16, 32, 64, 128 bits. Data type: integer, floating point Tile identical processing elements [© Prentice Hall] Spring 2006 EE VLSI Design II - © Kia Bazargan VLSI Design II – © Kia Bazargan

EE 5324 – VLSI Design II Part I, Appendix: FPGA Architectures
Kia Bazargan University of Minnesota Spring 2006 EE VLSI Design II - © Kia Bazargan

FPGA Architecture - Layout
Island FPGAs Array of functional units Horizontal and vertical routing channels connecting the functional units Versatile switch boxes Example: Xilinx, Altera Row-based FPGAs Like standard cell design Rows of logic blocks Routing channels (fixed width) between rows of logic Example: Actel FPGAs Spring 2006 EE VLSI Design II - © Kia Bazargan

FPGA Architecture: Functional Units
RAM blocks (Xilinx): implement function truth table Multiplexers (Actel): build Boolean functions using muxes Logic gates, flip-flops: Such as carry chains. Used for high-performance computations Address lines (input) output Spring 2006 EE VLSI Design II - © Kia Bazargan

Programmable Switch Elements
Used in connecting: The I/O of functional units to the wires A horizontal wire to a vertical wire Two wire segments to form a longer wire segment Spring 2006 EE VLSI Design II - © Kia Bazargan

Programmable Switch Elements: Implementation
SRAM connected to the gate of a transistor (Xilinx) Fuse / Anti Fuse (Actel) symbol implementation Note: Switches degrade the signals  slow down symbol implementation Spring 2006 EE VLSI Design II - © Kia Bazargan

Routing Channels Note: fixed channel widths (tracks) Should “predict” all possible connectivity requirements when designing the FPGA chip Channel -> track -> segment Segment length? Long: carry the signal longer, less “concatenation” switches, but might waste track Short: local connections, slow for longer connections segment track channel Spring 2006 EE VLSI Design II - © Kia Bazargan

Switch Boxes Ideally, provide switches for all possible connections Trade-off: Too many switches: Large area Complex to program Too few switches: Cannot route signals One possible solution Xilinx 4000 Spring 2006 EE VLSI Design II - © Kia Bazargan

Programming How to access all programmable elements? Pin limitation Feasibility of access (Actel example) Are there “invalid” configurations? - Chain all config bits in a shift register or use pipelining - Partition the elements into subsets, treat each as a memory block - Consider the problem when designing the FPGA architecture - Carefully schedule the programming - Yes! If two functional units drive same line - Avoid at architectural design or when prog Spring 2006 EE VLSI Design II - © Kia Bazargan

Programming (cont.) Too much detail! (tens of bits for each cell/switch block) Automated placement, routing and programming Design a simple structure so that tools can handle Partially reconfigurable? Extra control circuitry, more flexibility Runtime reconfigurable? (avoid conflicts with running components) Spring 2006 EE VLSI Design II - © Kia Bazargan

Pros and Cons General architecture Slower than ASIC Less logic capacity (solution: reuse silicon area through reconfiguration) Flexible Customization helps Instantiate many small processing elements  parallel processing Some operations faster (e.g., constant multiplication, bit-wise operations) More operations in parallel  reduce clock speed  reduce power consumption Spring 2006 EE VLSI Design II - © Kia Bazargan

New Challenges Balance between elements Data memory Configuration memory Special-purpose functional units Fine- vs. coarse-grain functional units Communication bandwidth Fast automatic tools Versatile libraries Spring 2006 EE VLSI Design II - © Kia Bazargan

EE 5324 – VLSI Design II Part I: Introduction Kia Bazargan

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EE 5324 – VLSI Design II Part I: Introduction Kia Bazargan

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