Computer Architecture Processor: Datapath

Computer Architecture Processor: Datapath
Dr. Hadi AL Saadi Faculty Of Information Technology University of Petra 4/6/2019 Dr. Hadi Hassan Computer architecture

Dr. Hadi Hassan Computer architecture
Processor: Datapath Processor Datapath Generic Execution Stages MIPS Execution Stages Constructing Datapath 4/6/2019 Dr. Hadi Hassan Computer architecture

Building a Processor: Datapath & Control Two major components for a processor: Datapath Collection of components that process data Performs the arithmetic, logical and memory operations Control Tells the datapath, memory, and I/O devices what to do according to program instructions 4/6/2019 Dr. Hadi Hassan Computer architecture

Components of the Datapath
Combinational Elements ALU, Adder Immediate extender Multiplexers Storage Elements Instruction memory Data memory PC register Register file Clocking methodology Timing of writes A L U ALU control ALU result zero 32 overflow Extend 32 16 ExtOp m u x 1 select 32 Address Instruction Memory Data Memory Address Data_in Data_out Mem Read Write 32 clk PC 32 clk clk Registers RA RB BusA RegWrite BusB RW 5 32 BusW clk 4/6/2019 Dr. Hadi Hassan Computer architecture

Register Element Register Similar to the D-type Flip-Flop n-bit input and output Write Enable (WE): Enable / disable writing of register Negated (0): Data_Out will not change Asserted (1): Data_Out will become Data_In after clock edge Edge triggered Clocking Register output is modified at clock edge Register Data_In Clock Write Enable n bits Data_Out WE 4/6/2019 Dr. Hadi Hassan Computer architecture

MIPS Register File Register File consists of 32 × 32-bit registers BusA and BusB: 32-bit output busses for reading 2 registers BusW: 32-bit input bus for writing a register when RegWrite is 1 Two registers read and one written in a cycle Registers are selected by: RA selects register to be read on BusA RB selects register to be read on BusB RW selects the register to be written Clock input The clock input is used ONLY during write operation During read, register file behaves as a combinational logic block RA or RB valid => BusA or BusB valid after access time Register File RA RB BusA RegWrite BusB RW 5 32 BusW Clock 4/6/2019 Dr. Hadi Hassan Computer architecture

Clocking Methodology Clocks are needed in a sequential logic to decide when a state element (register) should be updated To ensure correctness, a clocking methodology defines when data can be written and read We assume edge-triggered clocking All state changes occur on the same clock edge Data must be valid and stable before arrival of clock edge Edge-triggered clocking allows a register to be read and written during same clock cycle Combinational logic Register 1 Register 2 clock rising edge falling edge 4/6/2019 Dr. Hadi Hassan Computer architecture

MIPS Processor: Implementation
Simplest possible implementation of a subset of the core MIPS ISA: Arithmetic and Logical operations add, sub, and, or, addi, andi, ori, slt Data transfer instructions lw, sw Branches beq, bne Shift instructions (sll, srl) and J-type instructions (j) will not be discussed here Left as exercises  4/6/2019 Dr. Hadi Hassan Computer architecture

Recap: Instruction Execution Cycle Fetch: Get instruction from memory Address is in Program Counter (PC) Register Decode: Find out the operation required Operand Fetch: Get operand(s) needed for operation Execute: Perform the required operation Result Write (WriteBack): Store the result of the operation Instruction Fetch Decode Operand Execute Result Write Next Instruction 4/6/2019 Dr. Hadi Hassan Computer architecture

Instruction Fetching Datapath WriteBk Memory ALU Decode Fetch We can now assemble the datapath from its components For instruction fetching, we need … Program Counter (PC) register Instruction Memory Adder for incrementing PC Improved datapath increments upper 30 bits of PC by 1 32 Address Instruction Memory 30 PC 00 +1 Improved Datapath next PC clk PC 32 Address Instruction Memory 4 A d next PC clk The least significant 2 bits of the PC are ‘00’ since PC is a multiple of 4 Datapath does not handle branch or jump instructions 4/6/2019 Dr. Hadi Hassan Computer architecture

Element: Instruction Memory WriteBk Memory ALU Decode Fetch Storage element for the instructions Recall: sequential circuit Has an internal state that stores information Clock signal is assumed and not shown Supply instructions given the address Given instruction address M as input, the memory outputs the content at address M Conceptual diagram of the memory layout is given on the right  Instruction Memory Address Memory 2048 2052 2056 andi $1, $4, 0xF sll $4, $3, 2 add $3, $1, $2 …… ……….. 4/6/2019 Dr. Hadi Hassan Computer architecture

The Idea of Clocking WriteBk Memory ALU Decode Fetch It seems that we are reading and updating the PC at the same time: How can it works properly? Magic of clock: PC is read during the first half of the clock period and it is updated with PC+4 at the next rising clock edge Add PC 4 Read address Instruction memory In Clk Time PC 100 104 108 112 In 116 4/6/2019 Dr. Hadi Hassan Computer architecture

Decode Stage: Requirement WriteBk Memory ALU Decode Fetch Instruction Decode Stage: Gather data from the instruction fields: Read the opcode to determine instruction type and field lengths Read data from all necessary registers Can be two (e.g. add), one (e.g. addi) or zero (e.g. j) Input from previous stage (Fetch): Instruction to be executed Output to the next stage (ALU): Operation and the necessary operands 4/6/2019 Dr. Hadi Hassan Computer architecture

Decode Stage: Block Diagram
WriteBk Memory ALU Decode Fetch Register Number Fetch Stage Execute Stage Data 5 Read register 1 Read data 1 Inst. 5 Read register 2 Operands Register File 5 Write register Read data 2 Collection of registers, known as register file 4/6/2019 Dr. Hadi Hassan Computer architecture

Element: Register File WriteBk Memory ALU Decode Fetch A collection of 32 registers: Each is 32-bit wide and can be read/written by specifying register number Read at most two registers per instruction Write at most one register per instruction RegWrite is a control signal to indicate: Writing of register 1(True) = Write, 0 (False) = No Write Read register 1 register 2 Write register data data 1 data 2 RegWrite Data Register Number File 5 32 Dr. Hadi Hassan Computer architecture 4/6/2019

Datapath for R-type Instructions
WriteBk Memory ALU Decode Fetch Op6 Rs5 Rt5 Rd5 funct6 sa5 32 Address Instruction Memory 30 PC 00 +1 Registers RA RB BusA BusB RW BusW 5 Rs Rt Rd A L U 32 ALU result clk Rs and Rt fields select two registers to read. Rd field selects register to write BusA & BusB provide data input to ALU. ALU result is connected to BusW Same clock updates PC and Rd register Control signals ALUCtrl is derived from the funct field because Op = 0 for R-type RegWrite is used to enable the writing of the ALU result 4/6/2019 Dr. Hadi Hassan Computer architecture

Decode Stage: R-Type Instruction WriteBk Memory ALU Decode Fetch add $8, $9, $10 Inst [25:21] 5 Read register 1 Read data 1 32 content of register $9 5 Read register 2 Inst [20:16] Register File 31:26 opcode 25:21 rs 20:16 rt 15:11 rd 10:6 shamt funct 5:0 5 Write register 000000 01001 01010 01000 00000 100000 Inst [15:11] Read data 2 content of register $10 Write data RegWrite Result to be stored (produced by later stage) Notation: Inst [Y:X] = bits X to Y in Instruction 4/6/2019 Dr. Hadi Hassan Computer architecture

Datapath for I-type ALU Instructions
WriteBk Memory ALU Decode Fetch Op6 Rs5 Rt5 immediate16 32 Address Instruction Memory 30 PC 00 +1 RegWrite 5 Registers RA RB BusA BusB RW BusW Rs Rt 32 ALU result A L U Extender Imm16 clk Same clock edge updates PC and Rt Rt selects register to write, not Rd Second ALU input comes from the extended immediate. RB and BusB are not used Control signals ALUCtrl is derived from the Op field RegWrite is used to enable the writing of the ALU result ExtOp is used to control the extension of the 16-bit immediate 4/6/2019 Dr. Hadi Hassan Computer architecture

Decode Stage: I-Type Instruction WriteBk Memory ALU Decode Fetch addi $21, $22, -50 31:26 opcode 25:21 rs 20:16 rt Inst [25:21] 5 Read register 1 Read data 1 32 Content of register $22 5 Read register 2 Inst [20:16] Register File 5 Write register 001000 10110 10101 Inst [15:11] Read data 2 Write data Immediate 15:0 RegWrite Problems: Destination $21 is in the "wrong position" Read Data 2 is an immediate value, not from register 4/6/2019 Dr. Hadi Hassan Computer architecture

Recap: Multiplexer WriteBk Memory ALU Decode Fetch Function: Selects one input from multiple input lines Inputs: n lines of same width Control: m bits where n = 2m Output: Select ith input line if control=i Control m MUX in0 . out inn-1 Control=0  select in0 Control=3  select in3 4/6/2019 Dr. Hadi Hassan Computer architecture

Combining R-type & I-type Datapaths
WriteBk Memory ALU Decode Fetch A L U ALU result 32 Registers RA RB BusA BusB RW 5 BusW Address Instruction Memory 30 PC 00 +1 Rs Rd Extender Imm16 Rt RegWrite ALUCtrl A mux selects RW as either Rt or Rd Another mux selects 2nd ALU input as either data on BusB or the extended immediate 1 1 clk ALUSrc RegDst ExtOp Control signals ALUCtrl is derived from either the Op or the funct field RegWrite enables the writing of the ALU result ExtOp controls the extension of the 16-bit immediate RegDst selects the register destination as either Rt or Rd ALUSrc selects the 2nd ALU source as BusB or extended immediate 4/6/2019 Dr. Hadi Hassan Computer architecture

Decode Stage: Choice in Data 2
WriteBk Memory ALU Decode Fetch addi $21, $22, -50 31:26 opcode 25:21 rs 20:16 rt Inst [25:21] 5 Read register 1 Read data 1 32 5 Inst [20:16] Read register 2 Register File 5 Write register 001000 10110 10101 MUX Read data 2 MUX Write data Inst [15:11] Immediate 15:0 RegWrite RegDst ALUSrc: A control signal to choose either "Read data 2" or the sign extended Inst[15:0] as the second operand ALUSrc Sign Extend Inst [15:0] 16 32 Solution (Rd. Data 2): Use a multiplexer to choose the correct operand 2. Sign extend the 16-bit immediate value to 32-bit 4/6/2019 Dr. Hadi Hassan Computer architecture

Controlling ALU Instructions WriteBk Memory ALU Decode Fetch A L U ALUCtrl ALU result 32 Registers RA RB BusA RegWrite = 1 BusB RW 5 BusW Address Instruction Memory 30 PC 00 +1 Rs Rd Extender ExtOp Imm16 Rt 1 For R-type ALU instructions, RegDst is ‘1’ to select Rd on RW and ALUSrc is ‘0’ to select BusB as second ALU input. The active part of datapath is shown in green ALUSrc = 0 RegDst = 1 clk clk A L U ALUCtrl ALU result 32 Registers RA RB BusA RegWrite = 1 BusB RW 5 BusW Address Instruction Memory 30 PC 00 +1 Rs Rd Extender ExtOp Imm16 Rt 1 For I-type ALU instructions, RegDst is ‘0’ to select Rt on RW and ALUSrc is ‘1’ to select Extended immediate as second ALU input. The active part of datapath is shown in green RegDst = 0 ALUSrc = 1 4/6/2019 Dr. Hadi Hassan Computer architecture

Adding Data Memory to Datapath
WriteBk Memory ALU Decode Fetch lw Rt, imm16(Rs) # Rt = MEMORY[Rs+imm16] sw Rt, imm16(Rs) # MEMORY[Rs+imm16] = Rt A data memory is added for load and store instructions 32 A L U ALUCtrl Registers RA RB BusA Reg Write BusB RW 5 BusW Address Instruction Memory 30 PC 00 +1 Rs Rd E ExtOp Imm16 Rt 1 RegDst ALUSrc MemRead MemWrite MemtoReg 32 ALU result 1 Data Memory Address Data_in Data_out 32 clk ALU calculates data memory address A 3rd mux selects data on BusW as either ALU result or memory data_out Additional Control signals MemRead for load instructions MemWrite for store instructions MemtoReg selects data on BusW as ALU result or Memory Data_out BusB is connected to Data_in of Data Memory for store instructions 4/6/2019 Dr. Hadi Hassan Computer architecture

Controlling the Execution of Load
WriteBk Memory ALU Decode Fetch lw Rt, imm16(Rs) # Rt = MEMORY[Rs+imm16] ExtOp = 1 ALUCtrl = ADD MemRead = 1 MemWrite = 0 ALUSrc = 1 Data Memory Address Data_in Data_out 32 A L U Registers RA RB BusA BusB RW 5 BusW Instruction 30 PC 00 +1 Rs Rd E Imm16 Rt 1 ALU result 32 MemtoReg = 1 RegDst = 0 clk RegWr = 1 RegDst = ‘0’ selects Rt as destination register RegWrite = ‘1’ to enable writing of register file ExtOp = 1 to sign-extend Immmediate16 to 32 bits ALUSrc = ‘1’ selects extended immediate as second ALU input ALUCtrl = ‘ADD’ to calculate data memory address as Reg(Rs) + sign-extend(Imm16) MemRead = ‘1’ to read data memory MemtoReg = ‘1’ places the data read from memory on BusW Clock edge updates PC and Register Rt 4/6/2019 Dr. Hadi Hassan Computer architecture

Decode Stage: Load Word Instruction WriteBk Memory ALU Decode Fetch Try it out: "lw $21, -50($22)" Do we need any modification? 31:26 opcode 25:21 rs 20:16 rt Inst [25:21] 5 Read register 1 Read data 1 32 5 Inst [20:16] Read register 2 Register File 5 Write register 100011 10110 10101 MUX Read data 2 MUX Write data Inst [15:11] Immediate 15:0 RegWrite RegDst ALUSrc Sign Extend Inst [15:0] 16 32 4/6/2019 Dr. Hadi Hassan Computer architecture

Controlling the Execution of Store
WriteBk Memory ALU Decode Fetch sw Rt, imm16(Rs) # MEMORY[Rs+imm16] = Rt ExtOp = 1 ALUCtrl = ADD MemRead = 0 MemWrite = 1 ALUSrc = 1 Data Memory Address Data_in Data_out 32 A L U Registers RA RB BusA BusB RW 5 BusW Instruction 30 PC 00 +1 Rs Rd E Imm16 Rt 1 ALU result 32 MemtoReg = X clk RegDst = X RegWr = 0 RegDst = ‘X’ because no register is written RegWrite = ‘0’ to disable writing of register file ExtOp = 1 to sign-extend Immmediate16 to 32 bits ALUSrc = ‘1’ selects extended immediate as second ALU input ALUCtrl = ‘ADD’ to calculate data memory address as Reg(Rs) + sign-extend(Imm16) MemWrite = ‘1’ to write data memory MemtoReg = ‘X’ because don’t care what data is put on BusW Clock edge updates PC and Data Memory 4/6/2019 Dr. Hadi Hassan Computer architecture

Adding Jump and Branch to Datapath
WriteBk Memory ALU Decode Fetch ALUCtrl Reg Write ExtOp RegDst ALUSrc Data Memory Address Data_in Data_out 32 A L U Registers RA RB BusA BusB RW 5 BusW Instruction PC 00 30 Rs Rd E Imm16 Rt 1 Imm26 ALU result clk +1 Jump or Branch Target Address Mem Read toReg Next PC Bne Beq J PCSrc zero Additional Control Signals J, Beq, Bne for jump and branch instructions Zero flag of the ALU is examined PCSrc = 1 for jump & taken branch Next PC logic computes jump or branch target instruction address 4/6/2019 Dr. Hadi Hassan Computer architecture

Controlling the Execution of Jump
WriteBk Memory ALU Decode Fetch 30 Jump Target Address Next PC Bne = 0 Beq = 0 J = 1 PCSrc = 1 30 ALU result 32 1 +1 Imm26 Imm16 zero Instruction Memory Registers Rs 5 32 Data Memory Address Data_in Data_out RA BusA 30 A L U 32 PC 00 Instruction 32 32 Rt 5 1 RB Address BusB 1 1 32 32 Rd RW E Mem toReg = x BusW ALUCtrl = x clk RegDst = x RegWr = 0 ExtOp = x ALUSrc = x Mem Read = 0 Mem Write = 0 J = 1 to control jump. Next PC outputs Jump Target Address We don’t care about RegDst, ExtOp, ALUSrc, ALUCtrl, and MemtoReg MemRead, MemWrite, and RegWrite are 0 Clock edge updates PC register only

Controlling the Execution of Branch
WriteBk Memory ALU Decode Fetch 30 Branch Target Address Next PC Bne = 0 Beq = 1 J = 0 PCSrc = 1 30 ALU result 32 1 +1 Imm26 Imm16 Zero = 1 Instruction Memory Registers Rs 5 32 Data Memory Address Data_in Data_out RA BusA 30 A L U 32 PC 00 Instruction 32 32 Rt 5 1 RB Address BusB 1 1 32 32 Rd RW BusW E Mem toReg = x ALUCtrl = SUB clk RegDst = x RegWr = 0 ExtOp = x ALUSrc = 0 Mem Read = 0 Mem Write = 0 Either Beq = 1 or Bne depending on opcode Next PC outputs branch target address PCSrc = 1 if branch is taken ALUSrc = 0 to select value on BusB RegWrite, MemRead, and MemWrite are 0 ALUCtrl = SUB to generate Zero Flag Clock edge updates PC register only

Decode Stage: Branch Instruction WriteBk Memory ALU Decode Fetch Example: "beq $9, $0, 3" Need to calculate branch outcome and target at the same time! We will tackle this problem in the ALU Stage  31:26 opcode 25:21 rs 20:16 rt Read register 1 register 2 Write register data data 1 data 2 5 Inst [25:21] Inst [20:16] Inst [15:11] MUX RegDst Inst [15:0] ALUSrc RegWrite Sign Extend 16 32 32 Register File 000100 01001 00000 Immediate 15:0 4/6/2019 Dr. Hadi Hassan Computer architecture

ALU Stage: Requirement WriteBk Memory ALU Decode Fetch Instruction ALU Stage: ALU = Arithmetic-Logic Unit Perform the real work for most instructions here Arithmetic (e.g. add, sub), Shifting (e.g. sll), Logical (e.g. and, or) Memory operation (e.g. lw, sw): Address calculation Branch operation (e.g. bne, beq): Perform register comparison and target address calculation Input from previous stage (Decode): Operation and Operand(s) Output to the next stage (Memory): Calculation result 4/6/2019 Dr. Hadi Hassan Computer architecture

ALU Stage: Block Diagram
WriteBk Memory ALU Decode Fetch Decode Stage Memory Stage Operands ALU result ALU Logic to perform arithmetic and logical operations 4/6/2019 Dr. Hadi Hassan Computer architecture

Element: Arithmetic Logical Unit WriteBk Memory ALU Decode Fetch ALU (Arithmetic-logical unit) Combinational logic to implement arithmetic and logical operations Inputs: Two 32-bit numbers Control: 4-bit to decide the particular operation Outputs: Result of arithmetic/logical operation A 1-bit signal to indicate whether result is zero ALU result ALUcontrol 4 isZero? A B A op B (A op B) == 0? ALUcontrol Function 0000 AND 0001 OR 0010 add 0110 subtract 0111 slt 1100 NOR 4/6/2019 Dr. Hadi Hassan Computer architecture

ALU Stage: Non-Branch Instructions
WriteBk Memory ALU Decode Fetch We can handle non-branch instructions easily: add $8, $9, $10 ALUcontrol Inst [25:21] 5 Read register 1 Read data 1 4 5 Inst [20:16] Read register 2 isZero? Register File ALU 31:26 opcode 25:21 rs 20:16 rt 15:11 rd 10:6 shamt funct 5:0 5 Write register ALU result 000000 01001 01010 01000 00000 100000 MUX Read data 2 MUX Write data Inst [15:11] RegWrite RegDst ALUSrc Sign Extend ALUcontrol: Set using opcode + funct field (more in next lecture) Inst [15:0] 16 32 4/6/2019 Dr. Hadi Hassan Computer architecture

ALU Stage: Brach Instructions WriteBk Memory ALU Decode Fetch Branch instruction is harder as we need to perform two calculations: Example: "beq $9, $0, 3" Branch Outcome: Use ALU unit to compare the register The 1-bit "isZero?" signal is enough to handle equal / not equal check (how?) Branch Target Address: Introduce additional logic to calculate the address Need PC (from Fetch Stage) Need Offset (from Decode Stage) 4/6/2019 Dr. Hadi Hassan Computer architecture

E.g. "beq $9, $0, 3" Complete ALU Stage MUX PCSrc: PCSrc MUX RegDst
WriteBk Memory ALU Decode Fetch PC Add 4 MUX Add Left Shift 2-bit PCSrc: Control Signal to select between (PC+4) or Branch Target 000100 01001 00000 Immediate 15:0 31:26 opcode 25:21 rs 20:16 rt Read register 1 register 2 Write register data data 1 data 2 Register File 5 Inst [25:21] Inst [20:16] Inst [15:11] MUX RegDst Inst [15:0] ALUSrc RegWrite Sign Extend 16 32 ALU result ALUcontrol 4 isZero? PCSrc E.g. "beq $9, $0, 3" 4/6/2019 Dr. Hadi Hassan Computer architecture

Memory Stage: Requirement WriteBk Memory ALU Decode Fetch Instruction Memory Access Stage: Only the load and store instructions need to perform operation in this stage: Use memory address calculated by ALU Stage Read from or write to data memory All other instructions remain idle Result from ALU Stage will pass through to be used in Result Store (Writeback) stage if applicable Input from previous stage (ALU): Computation result to be used as memory address (if applicable) Output to the next stage (Writeback): Result to be stored (if applicable) 4/6/2019 Dr. Hadi Hassan Computer architecture

Memory Stage: Block Diagram
WriteBk Memory ALU Decode Fetch MemWrite ALU Stage Result Store Stage Address Result Read Data Write Data Data Memory MemRead Memory which stores data values 4/6/2019 Dr. Hadi Hassan Computer architecture

Element: Data Memory WriteBk Memory ALU Decode Fetch Storage element for the data of a program Inputs: Memory Address Data to be written (Write Data) for store instructions Control: Read and Write controls; only one can be asserted at any point of time Output: Data read from memory (Read Data) for load instructions Data Memory Address Read Write MemRead MemWrite 4/6/2019 Dr. Hadi Hassan Computer architecture

Memory Stage: Load Instructions WriteBk Memory ALU Decode Fetch Only relevant parts of Decode & ALU Stages are shown lw $21, -50($22) 000100 01001 00000 Immediate 15:0 31:26 opcode 25:21 rs 20:16 rt ALUcontrol Inst [25:21] 4 RR1 RR2 WR WD RD1 RD2 Registers 5 RegWrite Inst [20:16] Address Write Data MemRead MemWrite Memory Read ALU 100011 10110 10101 MUX ALU result MUX Inst [15:11] RegDst ALUSrc Sign Extend Inst [15:0] 16 32 4/6/2019 Dr. Hadi Hassan Computer architecture

Memory Stage: Store Instructions WriteBk Memory ALU Decode Fetch Need Read Data 2 (Decode) as the Write Data sw $21, -50($22) 000100 01001 00000 Immediate 15:0 31:26 opcode 25:21 rs 20:16 rt ALUcontrol Inst [25:21] 4 RR1 RR2 WR WD RD1 RD2 Registers 5 RegWrite Inst [20:16] Address Write Data MemRead MemWrite Memory Read ALU 101011 10110 10101 MUX ALU result MUX Inst [15:11] RegDst Sign Extend Inst [15:0] 16 32 4/6/2019 Dr. Hadi Hassan Computer architecture

Result Write Stage: Requirement WriteBk Memory ALU Decode Fetch Instruction Register Write Stage: Most instructions write the result of some computation into a register Examples: arithmetic, logical, shifts, loads, set-less-than Need destination register number and computation result Exceptions are stores, branches, jumps: There are no results to be written These instructions remain idle in this stage Input from previous stage (Memory): Computation result either from memory or ALU 4/6/2019 Dr. Hadi Hassan Computer architecture

Result Write Stage: Block Diagram WriteBk Memory ALU Decode Fetch Memory Stage 5 Read register 1 Read data 1 5 Read register 2 Registers 5 Write register Read data 2 Result Write data Result Write stage has no additional element: Basically just route the correct result into register file The Write Register number is generated way back in the Decode Stage 4/6/2019 Dr. Hadi Hassan Computer architecture

Result Write Stage: Routing WriteBk Memory ALU Decode Fetch add $8, $9, $10 ALUcontrol Inst [25:21] 4 RR1 RR2 WR WD RD1 RD2 Registers 5 RegWrite MemWrite Inst [20:16] ALU 31:26 opcode 25:21 rs 20:16 rt 15:11 rd 10:6 shamt funct 5:0 000000 01001 01010 01000 00000 100000 MUX ALU result Address MUX Data Memory MemToReg Inst [15:11] Read Data MUX Write Data Sign Extend Inst [15:0] 4/6/2019 Dr. Hadi Hassan Computer architecture

The Complete Datapath! We have just finished “designing” the datapath for a subset of MIPS instructions: Shifting and Jumping are not supported Check your understanding: Take the complete datapath and play the role of controller: See how supported instructions are executed Figure out the correct control signals for the datapath elements 4/6/2019 Dr. Hadi Hassan Computer architecture

Complete Datapath Instruction Memory PC Add 4 MUX Instruction Add Left Shift 2-bit Address PCSrc ALUcontrol Inst [25:21] 4 5 RR1 RD1 5 Inst [20:16] is0? MemWrite RR2 Registers ALU ALUSrc 31:26 opcode 25:21 rs 20:16 rt 15:11 rd 10:6 shamt funct 5:0 5 WR 000000 01001 01010 01000 00000 100000 MUX ALU result Address MUX RD2 Data Memory WD MemToReg Inst [15:11] RegWrite Read Data MUX RegDst Write Data Sign Extend Inst [15:0] MemRead 4/6/2019 Dr. Hadi Hassan Computer architecture

Datapath: Generic Steps PC instruction memory +4 rt rs rd registers ALU Data imm Write Read Read 1. Instruction Fetch 2. Decode/ Register Read 3. ALU 4. Memory 5. Write Back 4/6/2019 Dr. Hadi Hassan Computer architecture

Main Control and ALU Control
Datapath Instruction Memory Op6 ALUCtrl funct6 A L U 32 Instruction Op6 RegDst RegWrite ExtOp ALUSrc MemRead MemWrite MemtoReg Beq Bne J Address Main Control ALU Control Input: 6-bit opcode field from instruction 6-bit function field from instruction ALU Control Output: ALUCtrl signal for ALU ALU Control Main Control Input: 6-bit opcode field from instruction Main Control Output: 10 control signals for the Datapath 4/6/2019 Dr. Hadi Hassan Computer architecture

Datapath Walkthroughs: ADD (1/2) add $r3,$r1,$r2 # r3 = r1+r2 Stage 1: Fetch this instruction, increment PC. Stage 2: Decode to find that it is an add instruction, then read registers $r1 and $r2. Stage 3: Add the two values retrieved in stage 2. Stage 4: Idle (nothing to write to memory). Stage 5: Write result of stage 3 into register $r3. 4/6/2019 Dr. Hadi Hassan Computer architecture

Datapath Walkthroughs: ADD (2/2) add $r3, $r1, $r2 PC instruction memory +4 registers ALU Data imm reg[2] reg[1] 2 1 3 add r3, r1, r2 reg[1]+reg[2] Write Read Read 4/6/2019 Dr. Hadi Hassan Computer architecture

Datapath Walkthroughs: SLTI (1/2) slti $r3,$r1,17 Stage 1: Fetch this instruction, increment PC. Stage 2: Decode to find it is an slti, then read register $r1. Stage 3: Compare value retrieved in stage 2 with the integer 17. Stage 4: Go idle. Stage 5: Write the result of stage 3 in register $r3. 4/6/2019 Dr. Hadi Hassan Computer architecture

Datapath Walkthroughs: SLTI (2/2) slti $r3, $r1, 17 PC instruction memory +4 registers ALU Data imm 17 reg[1] x 1 3 slti r3, r1, 17 reg[1]-17 Write Read Read 4/6/2019 Dr. Hadi Hassan Computer architecture

Datapath Walkthroughs: SW (2/2) sw $r3, 20($r1) PC instruction memory +4 registers ALU Data imm 20 reg[1] 3 1 x sw r3, 20(r1) reg[1]+20 Write Read MEM[r1+20]<-r3 reg[3] Read 4/6/2019 Dr. Hadi Hassan Computer architecture

Why Five Stages? Could we have a different number of stages? Yes, and other architectures do. So why does MIPS have five stages, if instructions tend to go idle for at least one stage? There is one instruction that uses all five stages: the load. 4/6/2019 Dr. Hadi Hassan Computer architecture

Datapath Walkthroughs: LW (1/2) lw $r3, 40($r1) Stage 1: Fetch this instruction, increment PC. Stage 2: Decode to find it is a lw, then read register $r1. Stage 3: Add 40 to value in register $r1 (retrieved in stage 2). Stage 4: Read value from memory address compute in stage 3. Stage 5: Write value found in stage 4 into register $r3. 4/6/2019 Dr. Hadi Hassan Computer architecture

Datapath Walkthroughs: LW (2/2) lw $r3, 40($r1) reg[3] PC instruction memory +4 registers ALU Data imm 40 reg[1] x 1 3 lw r3, 40(r1) reg[1]+40 Write Read r3<-MEM[r1+40] Read 4/6/2019 Dr. Hadi Hassan Computer architecture

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