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ROM ROM Capacity : PROM EEPROM : Output Enable connect to RD of uP
m+1 bit Address n+1 bit Data Am Dn ROM PROM EEPROM Capacity : : Output Enable connect to RD of uP : Chip Enable to Address decoder
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Timing Diagram for a Typical ROM
A0-Am D0-Dn OE falls to data valid Addr valid to data valid
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27XX EPROM PGM and VPP are used to programming 64 kbit 8 kbyte 16 kbit
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27XXX EPROM 128 kbit 16 kbyte 256 kbit 32 kbyte 512 kbit 64 kbyte
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28XX E2PROM 16 kbit 64 kbit 1026 kbit 4096 kbit 256 kbit 2 kbyte
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RAM (Random Access Memory)
The uP can read the data from RAM quickly, The uP can write new data quickly to RAM RAM forgets its data if power is turned off Two type of is available : Static RAM(SRAM): ff base, fast, expensive, low cap/vol, applied for cache , no refresh Dynamic RAM (DRAM): cap base, slow , low cost high capacity/volume , applied for main memory(pc) need refresh. RAM stands for random-access memory. RAM contains bytes of information, and the microprocessor can read or write to those bytes depending on whether the RD or WR line is signaled. One problem with today's RAM chips is that they forget everything once the power goes off. That is why the computer needs ROM
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RAM(Static) Capacity : RAM Data bus is Bidirectional : Read signal
m+1 bit Address n+1 bit Data Am Dn Capacity : RAM Data bus is Bidirectional : Read signal connect to MemRD of uP : Write signal connect to MemWR of uP : Chip Select to Address decoder
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Z80 CPU Pin Assignment
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Z80 Pin Description A15-A0 : D7-D0 : RD: WR:
Address bus (output, active high, 3-state). Used for accessing the memory and I/O ports During the refresh cycle the I is put on this bus. D7-D0 : Data Bus (input/output, active high, 3-state). Used for data exchanges with memory, I/O and interrupts. RD: Read (output, active Low, 3-state) indicates that the CPU wants to read data from memory or I/O WR: Write (output, active Low, 3-state) indicates that the CPU data bus holds valid data to be stored at the addressed memory or I/O location.
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Z80 Pin Description MREQ IORQ M1 RFSH
Memory Request (output, active Low, 3-state). Indicates memory read/write operation. See M1 IORQ Input/Output Request(output,active Low,3-state) Indicates I/O read/write operation. See M1 M1 Machine Cycle One (output, active Low). Together with MREQ indicates opcode fetch cycle Together with IORQ indicates an Int Ack cycle RFSH Refresh (output, active Low). Together with MREQ indicates refresh cycle. Lower 7-bits address is refresh address to DRAM
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Z80 Pin Description INT Interrupt Request (input, active Low).
Interrupt Request is generated by I/O devices. Checked at the end of the current instruction If flip-flop (IFF) is enabled. NMI Non-Maskable Interrupt (Input, negative edge-triggered). Higher priority than INT. Recognized at the end of the current Instruction Independent of the status of IFF Forces the CPU to restart at location 0066H.
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Z80 Pin Description BUSREQ Bus Request (input, active Low).
higher priority than NMI recognized at the end of the current machine cycle. forces the CPU address bus, data bus, and MREQ, IORQ, RD, and WR to high-imp. BUSACK Bus Acknowledge (output, active,Low) indicates to the requesting device that address, data, and control signals MREQ, IORQ, RD, and WR have entered their high-impedance states.
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Z80 Pin Description RESET Reset (input, active Low).
RESET initializes the CPU as follows: Resets the IFF Clears the PC and registers I and R Sets the interrupt status to Mode 0. During reset time, the address and data bus go to a high-impedance state And all control output signals go to the inactive state. must be active for a minimum of three full clock cycles before the reset operation is complete.
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Z80 CPU
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Z80 Programming Model
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Register Set A : Accumulator Register F : Flag register
Two sets of six general-purpose registers may be used individually as 8-bit A F B C D E H L (A’ F’ B’ C’ D’ E’ H’ L’) or in pairs as 16-bit registers AF BC DE HL (AF’ BC’ DE’ HL’) The Alternative registers (A’ F’ B’ C’ D’ E’ H’ L’) not visible to the programmer but can access via: EXX (BC)<->(BC') , (DE)<->(DE') , (HL)<->(HL') EX AF, AF ’ (AF)<->(AF') what is this instruction useful for?
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Register Set(cont) 4 16-bit registers hold memory address (pointers)
index registers (IX) and (IY) are 16-bit memory pointers 16 bit stack pointer (SP) Program counter (PC) PC points to the next opcode to be fetched from ROM when the µP places an address on the address bus to fetch the byte from memory, it then increments the program counter by one to the next location Special purpose registers I : Interrupt vector register. R : memory Refresh register
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Flag Register S Sign Flag (1:negativ)* Z Zero Flag (1:Zero)
H Half Carry Flag (1: Carry from Bit 3 to Bit 4)** P Parity Flag (1: Even) V Overflow Flag (1:Overflow)* N Operation Flag (1:previous Operation wassubtraction)** C Carry Flag (1: Carry from Bit n-1 to Bit n, with n length of operand) *: 2-complement number representation **: used in DAA-operation for BCD-arithmetic
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Instruction cycles, machine cycles and “T-states”
Instruction cycle is the time taken to complete the execution of an instruction Machine cycle is defined as the time required to complete one operation of accessing memory, accessing IO, etc. T-state = 1/f (f:Z80 Clock Frequency) f= 4MHZ T-state=0.25 uS
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Memory read/write cycle
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Adding One Wait State to an M1 Cycle
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Adding One Wait State to Any Memory Cycle
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IO read/write cycle During I/O operations a single wait state is automatically inserted
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Wait Signal the Z80 samples the wait signal during T2 if low then Z80 adds wait states to extend the machine cycle used to interface memories with slow response time Slow memory is low cost
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Interrupts There are two types of interrupts: non mask-able (NMI)
Could not be masked Jump to 0066H of memory mask-able(INT) Has 3 mode Can be set with the IM x Instruction IM 0 sets Interrupt mode 0 IM 1 sets Interrupt mode 1 IM 2 sets Interrupt mode 2
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Interrupt Modes Mode 0: Mode 1: Mode 2:
An 8 bit opcode is Fetched from Data BUS and executed The source interrupt device must put 8 bit opcode at data bus 8 bit opcode usually is RST p instructions Mode 1: A jump is made to address 0038h No value is required at data bus Mode 2: A jump is made to address (register I × value from interrupting device that puts at bus) I is high 8 bit of interrupt vector Value is low 8 bit of interrupt vector
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Z80 Memory connection CPU 16 bit address bus 64 k memory(max)
CPU 8 bit data bus 8 bit data width Generally should be connected Data to data Address to address Wr to wr Rd to rd Mreq to cs
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Memory connection (cont.)
If only one RAM chip Full size (64 kb capacity) RAM 64 kb Z80 CPU D7~D0 A15~A0
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Memory connection (cont.)
If RAM capacity was 32 kb A15 composed with MREQ RAM area is from 0000h to 7FFFh RAM 32 kb Z80 CPU D7~D0 A14~A0 A15
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Memory connection (cont.)
There is two 32 kb RAM Problem: Bus Conflict. The two memory chips will provide data at the same time when microprocessor performs a memory read. Solution: Use address line A15 as an “arbiter”. If A15 outputs a logic “1” the upper memory is enabled (and the lower memory is disabled) and vice-versa.
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Memory connection (cont.)
There is two 32 kb RAM A15 applied to select one RAM chip Two RAM area is from 0000h to 7FFFh (RAM1) and 8000h to FFFFh (RAM1) RAM 32 kb Z80 CPU D7~D0 A14~A0 A15
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Memory connection (cont.)
32 kb ROM and 32 kb RAM ROM doesn’t have wr signal ROM 32 kb Z80 CPU D7~D0 A14~A0 RAM A15
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Memory connection (cont.)
There is 4 memory chip A14 and A15 applied to chip selection ROM 16 kb D7~D0 A13~A0 RAM A15 A14 En S0 S1 Z80 CPU
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Address Bit Map Selects chip Selects location within chips A15 to A0
(HEX) AA AA 11 11 54 32 AAAA 1198 10 7654 3210 Memory Chip 0000h 3FFFh 00 00 00 11 0000 1111 ROM 4000h 7FFFh 01 00 01 11 RAM1 8000h BFFFh 10 00 10 11 RAM2 C000h FFFFh 11 00 RAM3
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Memory Map ROM Represents the memory type
Address area of each memory chip Empty area 0000h 3FFFh ROM 16k 4000h 7FFFh RAM1 8000h BFFFh RAM2 C000h FFFFh RAM3 ROM 16 kb D7~D0 A13~A0 RAM A15 A14 En S0 S1
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Memory Map ROM RAM2 RAM3 0000h 3FFFh Empty Area cann’t write and read
Read op. returns FFh value (usualy) Write op. cann’t store any value on it 0000h 3FFFh ROM 4000h 7FFFh Empty 8000h BFFFh RAM2 C000h FFFFh RAM3 ROM 16 kb D7~D0 A13~A0 A15 RAM A14 En S0 S1
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Memory Map ROM RAM 0000h 3FFFh Empty Area cann’t write and read
Read op. returns FFh value (usualy) Write op. cann’t store any value on it 0000h 3FFFh ROM 4000h 7FFFh Empty 8000h BFFFh RAM C000h FFFFh ROM 16 kb D7~D0 A13~A0 A15 RAM A14 En S0 S1
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Full and Partial Decoding
Full (exhaust) Decoding All of the address lines are connected to any memory/device to perform selection Absolute address : any memory location has one address Partial Decoding When some of the address lines are connected the memory/device to perform selection Using this type of decoding results into roll-over addresses (fold back or shading). roll-over address : any memory location has more than one address
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Partial Decoding A15~A12 has no connection
Then doesn’t play any role in addressing What is the Memory and Address Bit map? RAM 4 kb Z80 CPU D7~D0 A11~A0 X A15~A12
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Partial Decoding Roll-over Address
0000h 0FFFh RAM 1000h 1FFFh RAM’ 2000h 2FFFh 3000h 3FFFh F000h FFFFh Every memory location has more than one address For example first RAM location has addresses: 0000h 1000h 2000h 3000h ……………. F000h Roll-over Address RAM 4 kb Z80 CPU D7~D0 A11~A0 X A15~A12 A15 to A0 (HEX) AAAA 1111 5432 1198 10 7654 3210 Memory Chip X000h XFFFh xxxx 0000 RAM
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Partial Decoding X Z80 CPU A12 only connected to RAM
A13 has no connection What is the memory map? D7~D0 D7~D0 D7~D0 ROM 4 kb RAM 8 kb A12~A0 A11~A0 A12~A0 A13 X Z80 CPU A14 A15
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Partial Decoding 8 roll-over address for ROM
4 roll-over address for RAM ROM 4 kb Z80 CPU D7~D0 A11~A0 A12~A0 RAM 8 kb A14 A15 X A13 AAAA 1111 5432 1198 10 7654 3210 Memory Chip 0xxx 0000 ROM X0x0 X0x1 RAM
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Partial Decoding Conflict X RAM’ ROM ROM’ RAM Z80 CPU AAAA 1111 5432
0000h 1FFFh RAM’ 0FFFh ROM 1000h ROM’ 2000h 3FFFh 2FFFh 3000h 4000h 5FFFh 4FFFh 5000h 6000h 7FFFh 6FFFh 7000h 8000h 9FFFh RAM F000h FFFFh A000h BFFFh C000h DFFFh E000h Conflict ROM 4 kb Z80 CPU D7~D0 A11~A0 A12~A0 RAM 8 kb A14 A15 X A13 AAAA 1111 5432 1198 10 7654 3210 Memory Chip 0xxx 0000 4k ROM X0x0 X0x1 8k RAM
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Partial Decoding Conflict X ROM ROM’ RAM’ RAM Z80 CPU AAAA 1111 5432
0000h 1FFFh 0FFFh ROM 1000h ROM’ 2000h 3FFFh 2FFFh 3000h 4000h 5FFFh RAM’ 4FFFh 5000h 6000h 7FFFh 6FFFh 7000h 8000h 9FFFh F000h FFFFh A000h BFFFh C000h DFFFh RAM E000h ROM 4 kb Z80 CPU D7~D0 A11~A0 A12~A0 RAM 8 kb A14 A15 X A13 Conflict AAAA 1111 5432 1198 10 7654 3210 Memory Chip 0xxx 0000 4k ROM X1x0 X1x1 8k RAM
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Full (exhaustive) decoding
AAAA 1111 5432 1198 10 7654 3210 Memory Chip 0000 0001 ROM 0010 0111 RAM A12~A0 A12~A0 D7~D0 2764 EPROM 8k8 D7~D0 74138 Y0 Y1 Y2 Y3 Y6 Y4 Y7 Y5 C B A G2A G2B G1 A13 0000h-07FFh A12 0800h-0FFFh A11 7421 1000h-17FFh A10~A0 A10~A0 1800h-1FFFh D7~D0 2000h-27FFh 6116 RWM 2k8 A15 A14
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Partial decoding 74138 A12~A0 A12~A0 D7~D0 D7~D0 Y0 Y1 Y2 Y3 Y6 Y4 Y7
1111 5432 1198 10 7654 3210 Memory Chip 0000 0001 ROM 001x x000 x111 RAM A12~A0 A12~A0 D7~D0 2764 EPROM 8k8 D7~D0 74138 Y0 Y1 Y2 Y3 Y6 Y4 Y7 Y5 C B A G2A G2B G1 A15 0000h-1FFFh A14 2000h-3FFFh A13 A10~A0 A10~A0 D7~D0 6116 RWM 2k8 GND VCC
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1 Bit Memory With Separated I/O
D7-D0 D7 D1 D0 Din Din Din A11~A0 Dout A11~A0 Dout A11~A0 Dout A11-A0 A11-A0 A11-A0 2147 RWM 4k1 2147 RWM 4k1 2147 RWM 4k1
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What is the memory(addr. bit) map
A12~A0 D7~D0 2764 EPROM 8k8 74138 Y0 Y1 Y2 Y3 Y6 Y4 Y7 Y5 C B A G2A G2B G1 A15 0000h-1FFFh A14 2000h-3FFFh D7-D0 D7 D1 D0 A13 Din Din Din A11~A0 Dout A11~A0 Dout A11~A0 Dout A11-A0 A11-A0 A11-A0 2147 RWM 4k1 2147 RWM 4k1 2147 RWM 4k1 GND VCC
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Adding RAM & ROM
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Z80 Input Output Z80 at most could have 256 input port and 256 output
8 bit port address is placed on A7–A0 pin to select the I/O device OUT (n), A n is 8 bit port address Content of A is data OUT (C), r Content of C is a port address r is a data register IN A, (n) Data is transfered to A IN r (C) Content of Reg C is a port address Input data is transfered to r (data reg)
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Remember IO read/write cycle
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Z80 and simple output port
OUT (03), A Z80 CPU A14 A0 : D7 D6 WR IORQ A15 D5 D4 D3 D2 D1 D0 A 7 6 5 4 3 2 1 IOWR 74LS373 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 OE LE
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Z80 and simple input port IN A, (02) Z80 CPU 74LS244 A15 A14 : A0 D7
5V A14 : A0 D7 Y0 A0 D6 Y1 A1 D5 Y2 A2 Z80 CPU D4 Y3 A3 D3 Y4 74LS244 A4 D2 Y5 A5 D1 Y6 A6 D0 Y7 A7 G1 G2 IORQ RD A A A A A A A A IORD 7 6 5 4 3 2 1
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