1. Digital Signal Processing
J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept

2. Selection of an appropriate sequence of transfer function for the processing
Example:
Simulated ADC response
ADC gain = 1000
Delta charge injection:
Time Value
,34
,33
,33 ,2 ,2
FADCn n=50,250
Optimized to extract
physical quantities
(charge, etc.)
Processed: Original:
Fn ; n=z,N <= FADCn ; n=z,N
transfer function?
J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept

3. Example:The moving window deconvolution transfer function
For an arbitrary window of L samples :
F[n] = ai * FADC[n-i]
i=0,N L
a0 = 1
ai = 1/TAUpreamp i = 1, L-1
(TAUpreamp in units of the sampling period)
aL = /TAUpreamp
Properties
Transforms an exponential into
a rectangular function of L points.
J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept

4. Simplified implementation in favorable cases
In the previous example, ai = 1/TAUpreamp i = 1, L (equal weight factors)
The term with identical ai’s,: G[n] = ai * FADC[n-i]
i=1,L-1
Add the new element at the head
Reduces to :
G[n] = G[n-1] + a * (FADC[n-1] – FADC[n-L] )
Remove the out of range element at the tail
Value for the previous point
Hardware implementation:
Counter
Constant N-1
Sampling Clock A - B
Dual Port
Memory
Write address
Read Address
a * FADC[n-1]
Data In
a * FADC[n-L]
Data Out A - B
Accumulator +=
Sampling Clock
G[n]
J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept

5. Deconvolution in the presence of noise
Remark:
For series noise, the
RMS value of the noise
in the resulting function
is increased by a factor
SQRT(2)
Note: It can be demonstrated that the transfer function shown on the next slide will
yield the best estimate of the trend of the “flat” portion of the deconvolution
J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept

6. Floating average (boxcar) filter applied to the deconvolution result
Transfer function:
G[n] = aj * F[n-j]; aj = 1/K
j = 0, K -1
Example with K = 16; Note parameter K =>  Peaking time 
G[n]
J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept

7. Some interesting properties of the filter
1- For an input step function,
the resulting shape is a
symetrical trapeze with a
peaking time of K and a
flat-top equal to L - K
2- As long as the charge
collection in the detector
is shorter than L - K, the
pulse shape will reach its
full amplitude.
=> NO ballistic deficit
3- The S/N ratio is slighly
better than that of an
analog CR-(RC)n or
pseudo gaussian filter
of the same FWHM. K L
J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept

8. Performance summary of the « trapezoidal » filter
- The S/N of the trapezoidal signal is a few % better than that of a pseudo-gaussian
analog filter
For signal rise-times shorter than the parameter K, the filtered signal has zero
ballistic deficit. (Same filtered pulse height for all rise-times)
The trapezoidal signal has no « tail » . (Good behaviour for pile-up)
Other considerations:
As for its analog counterpart with pole-zero suppression, the transfer function
is not zero for the DC or low frequency components. It requires the equivalent
of a « baseline restorer », or double sampling.
J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept

9. Time measurement Example: the Constant Fraction Discriminator (CFD)
Principle: Compensates for the time walk associated with the pulse height. Tr
Threshold set at MAX * Fraction:
“Black” Threshold
“Blue” Threshold Δt
Same for all amplitudes if Tr is constant
If Tr is not constant: Use a “delay line clip” ≤ than the shortest rise time
Tr1
Not Clipped
Tclipped
Clipped
“Black” Threshold
“Blue” Threshold Δt
Same again! (in the case of a linear rise time)
J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept

10. Time measurement, digital CFD implementation example
Step 1: Clip the raw data samples:
F[n] = ai * FADC[n-i] ; (a0=1, aMinTr=-1) = FADC[n] – FADC[n-MinTr]
i=0,N
Step 2: Arm the “find Max” process when F[n] goes above a pre defined threshold (leading edge)
Step 3: Find the maximum value of F[n]
Step 4: Calculate the constant fraction threshold ( F[Max] * Fraction)
Step 5: Produce a delayed clipped pulse shape
Step 6: Find the two points of F[n] delayed on either side of the threshold level
Step 7: Interpolate the value between the two points
result: 1) Value of the index “n” at the crossover point
2) Time interpolation value (“vernier”) ( precision << sampling period)
=> “High resolution Time Stamp”
J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept

11. Timing resolution in the digital CFD
Sources of error in the presence of noise:
Error on the evaluation of the
maximum = Nrms
Error on the evaluation of the
signal amplitude = Nrms
Amplitude Tr
Error on the evaluation of the
fraction threshold = Nrms * Fraction
fraction threshold S Δt
Time
J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept

12. Timing resolution in the digital CFD (zoom)
Resulting error in the evaluation of time:
TError_rms = Nrms * (1+Fraction) * Tr/S Tr
error S
Notes:
- Valid for analog or digital CFD
- independant of digital sampling rate to first order
- Error may be much smaller than the sampling
rate for large signal to noise (S/Nrms) ratios
fraction threshold
Extra source of errors for the discrete sampling:
- linear intrapolation of the rise time function
Position of the sample with no noise
nominal Δt
Position of the sample with noise
J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept

13. The TIG-10 Module Characteristics: Form factor: VXI-C
Interface :a) Stand-alone: VME-A24D16
:b) System: 200 MHz source
synchronous LVDS
Number of channels:
Digitizers : 100 MHz 14-bit
Signal processing:
Raw data
- Trigger latency buffer
- Data sample buffers
Charge Channel:
- Preamplifier decay pole deconvolution
- Trapezoidal filter
- Baseline restorer
Timing channel
- Hit detector
- CFD
- Trigger generate / accept logic
Data flow/control:
- Parameters read/write
- Event builder
- Communication links
J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept

14. Example 4: the VF48 card, (Rev 0 shown)
48 Differencial Channels
FADCs:
- 10 bit, MS/sec
Interfaces
Serial LVDS
VME64
Signal processing:
7 Altera Cyclone FPGAs
Raw data segments
Hit detection
Charge calculation
Time stamp
Event formatting
Applications:
TPC readout
ILC prototypes
TACTIC detector
PET readout
Silicon and scintillation
detectors readout
ASIC preamp multiplexer readout (ALPHA)
J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept

15. Properties of the VF48 card
Form Factor : VME 6U
Number of channels : 48
Number of bits : 10 (12 bits under development)
Max sampling frequency : 65 MS/sec.
Max number of samples/event : 2048 (for each channel)
Interface: : 1) VME64X
2) Source synchronous serial, 200 mbits/sec, copper (RJ45)
Common system clock : From front panel connector or serial link
Local trigger signalling output : Front panel conector or serial link
Trigger accept input : «  «  « 
J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept

16. Example 3, TIGRESS DAQ architecture
Trigger decision
Run control (parameters)
System clock
Optional logic signals
Master
Communication links
Interface to computers
Sub Events,(one
clover or more)
System concentrators
TIG-C
Communication links
Event fragments,
(one crystal)
Local Collectors
TIG-10
Communication links
Trigger requests,
Data elements:
-pulse shapes
- charge
- time
- other “features”
720+ Channels
720 Signals + Aux.
Detectors
J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept

17. Example 2, TIG-C serial readout module, PCB, component layer
1 RJ45 master link connector
(820 Mbit/sec. Max)
VME64
12 RJ45 links connector
Altera Stratix FPGA
J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept