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J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept 12-14 2006 1 Digital Signal Processing.

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Presentation on theme: "J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept 12-14 2006 1 Digital Signal Processing."— Presentation transcript:

1 J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept 12-14 2006 1 Digital Signal Processing

2 J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept 12-14 20062 Selection of an appropriate sequence of transfer function for the processing Simulated ADC response ADC gain = 1000 Delta charge injection: Time Value 120 0,34 121 0,33 122 0,33 160 0,2 161 0,2 Processed: Original: F n ; n=z,N <= FADC n ; n=z,N transfer function? Example: FADC n n=50,250 Optimized to extract physical quantities (charge, etc.)

3 J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept 12-14 20063 Example:The moving window deconvolution transfer function F[n] = a i * FADC[n-i] i=0,N For an arbitrary window of L samples : a 0 = 1 a i = 1/TAU preamp i = 1, L-1 (TAU preamp in units of the sampling period) a L = -1 + 1/TAU preamp Properties Transforms an exponential into a rectangular function of L points. L

4 J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept 12-14 20064 Simplified implementation in favorable cases In the previous example, a i = 1/TAU preamp i = 1, L-1 (equal weight factors) The term with identical a i ’s,: G[n] = a i * FADC[n-i] i=1,L-1 Reduces to : G[n] = G[n-1] + a * (FADC[n-1] – FADC[n-L] ) Add the new element at the head Remove the out of range element at the tail Value for the previous point A - B Accumulator += Sampling Clock G[n] Hardware implementation: Counter Constant N-1 Sampling Clock A - B Dual Port Memory Write address Read Address a * FADC[n-1] Data In a * FADC[n-L] Data Out

5 J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept 12-14 20065 Deconvolution in the presence of noise Remark: For series noise, the RMS value of the noise in the resulting function is increased by a factor SQRT(2) Note: It can be demonstrated that the transfer function shown on the next slide will yield the best estimate of the trend of the “flat” portion of the deconvolution

6 J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept 12-14 20066 Floating average (boxcar) filter applied to the deconvolution result G[n] = a j * F[n-j]; a j = 1/K j = 0, K -1 Transfer function: Example with K = 16; Note parameter K => Peaking time G[n]

7 J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept 12-14 20067 Some interesting properties of the filter L K 1- For an input step function, the resulting shape is a symetrical trapeze with a peaking time of K and a flat-top equal to L - K 2- As long as the charge collection in the detector is shorter than L - K, the pulse shape will reach its full amplitude. => NO ballistic deficit 3- The S/N ratio is slighly better than that of an analog CR-(RC)n or pseudo gaussian filter of the same FWHM.

8 J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept 12-14 20068 Performance summary of the « trapezoidal » filter - The S/N of the trapezoidal signal is a few % better than that of a pseudo-gaussian analog filter - For signal rise-times shorter than the parameter K, the filtered signal has zero ballistic deficit. (Same filtered pulse height for all rise-times) - The trapezoidal signal has no « tail ». (Good behaviour for pile-up) Other considerations: As for its analog counterpart with pole-zero suppression, the transfer function is not zero for the DC or low frequency components. It requires the equivalent of a « baseline restorer », or double sampling.

9 J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept 12-14 20069 Time measurement Example: the Constant Fraction Discriminator (CFD) Principle: Compensates for the time walk associated with the pulse height. “Black” Threshold “Blue” Threshold ΔtΔtSame for all amplitudes if Tr is constant If Tr is not constant: Use a “delay line clip” ≤ than the shortest rise time “Black” Threshold “Blue” Threshold ΔtΔtSame again! (in the case of a linear rise time) Clipped Not Clipped Threshold set at MAX * Fraction: Tr Tr1 T clipped

10 J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept 12-14 200610 Time measurement, digital CFD implementation example Step 1: Clip the raw data samples: F[n] = a i * FADC[n-i] ; (a 0 =1, a MinTr =-1) = FADC[n] – FADC[n-MinTr] i=0,N Step 2: Arm the “find Max” process when F[n] goes above a pre defined threshold (leading edge) Step 3: Find the maximum value of F[n] Step 4: Calculate the constant fraction threshold ( F[Max] * Fraction) Step 5: Produce a delayed clipped pulse shape Step 6: Find the two points of F[n] delayed on either side of the threshold level Step 7: Interpolate the value between the two points result: 1) Value of the index “n” at the crossover point 2) Time interpolation value (“vernier”) ( precision << sampling period) => “High resolution Time Stamp”

11 J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept 12-14 200611 Timing resolution in the digital CFD ΔtΔt Tr Sources of error in the presence of noise: Amplitude Time fraction threshold Error on the evaluation of the maximum = Nrms Error on the evaluation of the fraction threshold = Nrms * Fraction Error on the evaluation of the signal amplitude = Nrms S

12 J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept 12-14 200612 Timing resolution in the digital CFD (zoom) ΔtΔt Tr fraction threshold S Extra source of errors for the discrete sampling: - linear intrapolation of the rise time function Notes: - Valid for analog or digital CFD - independant of digital sampling rate to first order - Error may be much smaller than the sampling rate for large signal to noise (S/Nrms) ratios Resulting error in the evaluation of time: TError_rms = Nrms * (1+Fraction) * Tr/S error Position of the sample with no noise Position of the sample with noise nominal

13 J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept 12-14 200613 The TIG-10 Module Characteristics: Form factor: VXI-C Interface :a) Stand-alone: VME-A24D16 :b) System: 200 MHz source synchronous LVDS Number of channels: 10 Digitizers : 100 MHz 14-bit Signal processing: Raw data - Trigger latency buffer - Data sample buffers Charge Channel: - Preamplifier decay pole deconvolution - Trapezoidal filter - Baseline restorer Timing channel - Hit detector - CFD - Trigger generate / accept logic Data flow/control: - Parameters read/write - Event builder - Communication links

14 J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept 12-14 200614 Example 4: the VF48 card, (Rev 0 shown) 48 Differencial Channels FADCs: - 10 bit, 20-65 MS/sec Interfaces - Serial LVDS - VME64 Signal processing: 7 Altera Cyclone FPGAs - Raw data segments - Hit detection - Charge calculation - Time stamp - Event formatting Applications: TPC readout - ILC prototypes - TACTIC detector - PET readout Silicon and scintillation detectors readout ASIC preamp multiplexer readout (ALPHA)

15 J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept 12-14 200615 Properties of the VF48 card Form Factor: VME 6U Number of channels: 48 Number of bits: 10 (12 bits under development) Max sampling frequency: 65 MS/sec. Max number of samples/event: 2048 (for each channel) Interface:: 1) VME64X 2) Source synchronous serial, 200 mbits/sec, copper (RJ45) Common system clock: From front panel connector or serial link Local trigger signalling output: Front panel conector or serial link Trigger accept input: « « «

16 J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept 12-14 200616 Example 3, TIGRESS DAQ architecture 720 Signals + Aux. 720+ Channels Local Collectors Communication links Detectors Communication links System concentrators Interface to computers Master Communication links Trigger requests, Data elements: -pulse shapes - charge - time - other “features” Event fragments, (one crystal) Sub Events,(one clover or more) Trigger decision Run control (parameters) System clock Optional logic signals TIG-10 TIG-C

17 J.P.Martin, Université de Montréal, ILC EndCap Meeting, Paris, Sept 12-14 200617 Example 2, TIG-C serial readout module, PCB, component layer 12 RJ45 links connector 1 RJ45 master link connector (820 Mbit/sec. Max) VME64 Altera Stratix FPGA


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