1. AN ENHANCED LOW POWER HIGH SPEED ADDER FOR ERROR TOLERANT APPLICATIONS BY K.RAJASHEKHAR, 121024009, VLSI Design.

2. INDEX Need of ETA ETA ETA Versions Comparisons Applications Conclusion

3. NEED OF ETA Increasingly huge data sets and the need for instant response require the adder to be large and fast. Many different types of fast adders, such as the CSK, CSL and CLA have been developed. For conventional digital circuit design, speed & power are tradeoff. ◦ Speed α power. For ETA, a new component to trade-off is introduced: the accuracy. If the system can accept some error, both power & speed can be improved. The new trade-off : power-speed-accuracy.

4. KEY TERMINOLOGIES Overall error (OE) – OE =| Rc − Re | Rc – correct result Re – eta result Accuracy (ACC): indicates how “correct” the output is for a particular input. Minimum acceptable accuracy (MAA):the accuracy of an acceptable output should be “high enough”. Acceptance probability (AP):AP = P(ACC > MAA), where P is the probability.

5. ETA In the conventional adder circuit, the delay is mainly attributed to the carry propagation chain along the critical path, from LSB to MSB. Also glitches in the carry propagation chain dissipate a significant proportion of dynamic power dissipation. Therefore, if the carry propagation can be eliminated or curtailed, a great improvement in speed performance and power consumption can be achieved.

6. ETA Versions ETA I ETA 11 ETA 11 M ETA 111 ETA I V

7. ETA- 1 First split the input operands into two parts: ◦ accurate part - several higher order bits ◦ inaccurate part - remaining lower order bits. Example : Take two 16 bit operands A = 1011001110011010 (45978) + B = 0110100100010011 (26899) 10001110010101101 (72877)

8. PROPOSED ARITHMETIC ADDITION  The above ETA sum (72863) decimal value relative to the conventional sum (72877) results in an error of 9 (1001).

9. HARDWARE IMPLEMENTATION OF ETA

10. (a)Overall Architecture of control block(b)CSGC

11. Carry-free addition block Modified XOR gate

12. AP OF ETAI WITH DIFFERENT MAA’S AND INPUT RANGES

13. 0000000000001111 0000000000001111 + + 0000000000001111 0000000000001111 0000000000001111 0000000000011110 ETA 1 ADDITION CONVENTIONAL FAULT ADDTN. EXAMPLE :

14. ETA-11 The proposed ETAII is an enhancement of earlier design, the ETAI, which has problem adding small number inputs.

15. 0000000000001111 0000000000001111 + + 0000000000001111 0000000000001111 0000000000001111 0000000000011110 ETA 1 ADDITIONETA 11 ADDITION Carry = AB => GENERATE

16. AP OF ETAII WITH DIFFERENT MAA’S AND INPUT RANGES

17. ETA -11 M In the new design, the higher bits should be more accurate than the lower bits as they play a more important role in representing a number. In this structure, the first three carry generators are cascaded together to generate the carry signals for the two highest blocks. In this way, the carry signal for the highest block is generated by the preceding 12 bits and the carry signal for the second block is generated by the preceding 8 bits and so on.

18. BLOCK DIAGRAM OF ETA- 11 M

19. ETA 111 Similar to ETA 1, the input bits are separated into accurate and inaccurate parts. Unlike ETA 1, the division need not to be predetermined. Division of no. of bits is done by Selector(S) circuit. Two types of adders : ◦ Full adder (FA) Speed adder (SA)  If the first three blocks are non zero (ETA I ) => higher 3 blocks become accurate part => last 5 blocks become inaccurate part  else (ETA 111 )  Higher 6 blocks –accurate part  last 2 blocks – inaccurate part

20. ARCHITECTURE OF ETA 111

21. PROPOSED ARITHMETIC ADDITION

22. Speed Adder(SA) Circuit Logic Circuit Selector(S)

23. AP OF ETA-III WITH DIFFERENT MAA’S AND INPUT RANGES

24. ETA -IV To overcome the short-comings of both ETAII and ETAIIM, ETA Type IV (ETAIV) is proposed.

25. AP OF ETAIV WITH DIFFERENT MAA’S AND INPUT RANGES

26. COMPARISONS

28. (a) Original sound (b) Sound after FFT and inverse FFT (c) Sound after FFT and inverse FFT (with ETAIV embedded)

29. APPLICATIONS In digital signal processing (DSP) systems. It can be widely used in multimedia systems such as sound and image processing. Portable devices such as cell phones and laptops.

30. CONCLUSION Thus low-power and high-speed ETA family is to a greater extend more competitive than the conventional adders seen in the market, especially in the low accuracy applications.

31. REFERENCES Melvin A. Breuer and Haiyang Zhu, “Error-tolerance and multi-media,” in Proc. of the 2006 International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2006. Zhu Ning, Zhang Weijia, Goh Wang Ling, Yeo Kiat Seng, and Kong Zhi Hui, “Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing”, accepted for publication in IEEE Transactions on Very Large Scale Integration Systems II. I.S. Chong and A. Ortega, ‘‘Hardware Testing for Error Tolerant Multimedia Compression Based on Linear Transforms,’’ Proc. 20 th IEEE Int’l Symp. Defect and Fault Tolerance in VLSI Systems (DFT 05), IEEE CS Press, pp. 523-534, 2005. Jayanthi, A.N. and C.S. Ravichandran, “Design of an Error Tolerant Adder”, American Journal of Applied Sciences 9 (6): 818-824, 2012 ISSN 1546-9239 © 2012 Science Publications Ning Zhu; Wang Ling Goh; Kiat Seng Yeo, “Ultra low-power high-speed flexible Probabilistic Adder for Error-Tolerant Applications” SoC Design Conference (ISOCC), 2011 International Publication Year: 2011, Page(s): 393 - 396 Ning Zhu; Wang Ling Goh; Gang Wang; Kiat Seng Yeo,“Enhanced low-power high- speed adder for error-tolerant application” SoC Design Conference (ISOCC), 2010 InternationalPublication Year: 2010, Page(s): 323 - 327

32. QUESTIONS ?

33. THANK YOU