TOPIC : RTD, SST UNIT 5 : BIST and BIST Architectures Module 5.2 Specific BIST Architectures.

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Presentation transcript:

TOPIC : RTD, SST UNIT 5 : BIST and BIST Architectures Module 5.2 Specific BIST Architectures

Random Test Data (RTD) In previous architectures, entire scan path is to be loaded with new data to apply a single test pattern to the CUT. To solve this problem, RTD BIST architecture is developed. It’s attributes are: distributed and embedded BIST architecture Boundary scan is present. Signature analyzers are used for both compression and test pattern generation.

Contd … RTD BIST architecture is shown in below figure: Random Test Data BIST architecture

Test process of RTD Registers R1, R2, R3 are loaded with a seed pattern by setting to scan mode. R1 cannot be loaded with all 0’s. The registers are then put into their test mode and held in this state while the circuit is tested. For each clock, R1 and R2 generate a new test pattern. R2 and R3 operate as a MISR.

Contd … The patterns generated by R2 are a function of the CUT logic since these patterns are the state of a MISR. Hence the problem with this technique is some binary patterns may be repeated and others may never be generated. The concept of RTD technique is that if the normal data in a circuit is suitably combined with some form of error capturing mechanism, it is sufficient to test a circuit.

Simultaneous Self Test (SST) It has the following attributes: No boundary scan Scan CUT architecture Distributed and embedded BIST architecture LFSR’s are not used Each storage cell in the CUT is modified to be a self- test storage cell.

Self-test Storage Cell It has 3 modes of operation: ◦ Normal mode ◦ Scan mode ◦ Test mode By applying appropriate clock signals and T, S i signals, different modes are selected.

Contd … For normal operation, the value of the system data signal D is loaded into the flip-flop by CK1. For scan operation, T is set to 0 and clock CK2 is used. For self-test operation, T is set to 1 and CK2 is again used. The new state of the flip-flop is equal to (D XOR S i ).

Contd … A circuit employing simultaneous self-test is shown: Simultaneous self-test BIST architecture

Contd … The scan path is first loaded with seed data. The circuit is then put into test mode and clocked a sufficient number of times to be adequately tested. After testing, the circuit is put back into the scan mode and the contents of the scan path are shifted out. If the final contents of the scan path is incorrect, faulty operation is detected.

Contd … During the test process, self-test scan path is simultaneously collecting test results from C and supplying test values to C. Since test data need not be shifted into the scan path, it leads to a very fast test process.