THEME 6: Frequency dividers. Digital counters with reduced counting modulus. Programmable digital counters. If the input pulses are more than K, the counter counts up to K and the next pulse turns it in zero state. Then it starts the counting from the beginning and so on. After every K input pulses an output signal is generated with K times smaller frequency than the frequency of the input signal. This defines the second main application of digital counters – as frequency dividers. The frequency divider has only one output from the last flip-flop and the frequency of the output pulses is K times smaller than the frequency of the input pulses. The modulus K here is called dividing coefficient. The order of the states of the counter does not matter when used as a frequency divider.  Increasing the counting modulus is realized by successive connection of integrated circuits of digital counters. There are three possible ways for realizing successive connection: - Asynchronous connection of digital counters - the input of the last significant digital counter integrated circuit is the input of the whole group, whereas the inputs of the rest counters are connected to the most significant output of previous circuits. DIGITAL ELECTRONICS

Example of asynchronous connection of digital counters Asynchronous connection of reversible counters. Although all integrated circuits are synchronous counters, the connections between them are asynchronous. Synchronous connection of digital counters. The circuit enable input (СЕ) of the last significant counter is common for the whole group, whereas the CE inputs of the rest counters are connected to the carry output of previous circuits. DIGITAL ELECTRONICS

Digital counters with reduced counting modulus are counters with K< 2 n. There are different ways to realize counter with reduced counting modulus. One of them is to reduce the higher inner states by introducing the state detector in the feedback from the outputs of the counter to its reset input. The modulus must be converted in binary code and connect the outputs corresponding to the ones in the binary number to the reset input through one or more logic gates. The detected state is dependant on the chosen counting modulus (К) and the type of the reset inputs for the particular counter. For counting modulus К and counter with master reset (MR) inputs the state detector must discover К-state, while for counters with synchronous reset (SR) inputs – it must discover (К-1)-state. The important in both cases is, the active level on the output of state detector to be the same as the active level of the reset inputs. DIGITAL ELECTRONICS

An example realization of digital counter with reduced counting modulus К=13 using the IC with Master reset input is shown on the figure below. The binary code of К=13 is (1101), so the ones are on the outputs Q 0,Q 2 and Q 3, whereat the signals for the state detector are taken. In this example the state detector is implemented by 4-inputs logic gate NAND. DIGITAL ELECTRONICS

Another example realization of digital counter with reduced counting modulus К=13 using the IC with synchronous reset input is shown on the next figure. Here the state detector must detect the number (К-1)=12, which binary code is (1100), so the ones are on the outputs Q 2 and Q 3, whereat the signals for the state detector are taken. In this example the state detector is implemented by 2-inputs logic gate NAND. DIGITAL ELECTRONICS

Another way for reducing counting modulus is to reduce the lower inner states of the counter by using digital counters with parallel load inputs. Such a counter is IC It consists of four flip-flops with parallel load inputs X A, X B, X C, X D and corresponding outputs Q A, Q B, Q C, Q D. It is a reversible (up/down) counter so it has separate up/down clock inputs - (Cc) and (Cи) respectively. It has also two carry outputs - (Qпc) and (Qпи), which level is normally high. When the counter has reached the maximum count state of 15/0 the next ‘1’ – ‘0’ transition of Cс/Cи will cause the signal on Qпc /Qпи going low. It will stay low until the clock goes high again. The counter may be preset by the parallel load inputs when the Xs input is low. It is reset by the MR input, when it is high. If one of the carry outputs (Qпс) or (Qпи) is connected to the Xs input, after the first counting cycle up to 15 or down to 0, the modulus of counting will be changed according to the information fed on the inputs X A, X B, X C, X D. DIGITAL ELECTRONICS

One example where the carry output TC+ is connected to the L input and on the inputs D 3 -D 0 the information is set to Here, after the first full cycle of counting, the digital counter will continue with new reduced counting modulus K=13. As could be seen from the given timing diagram the lower inner states will be reduced. DIGITAL ELECTRONICS

It is also possible to reduce the counting modulus by connecting the carry output (Qпи) to the Xs input. Then after the first counting down from 15 to 0, the counting modulus will be reduced according to the information (the number N) given on the inputs X A, X B, X C, X D. In this case the higher inner states will be reduced. Then in accumulating mode (up) the counting modulus could be determined from the equation К=2 n -(N+1), while in subtracting mode (down) the counting modulus will be К=N. In such way it is possible to realized so called programmable digital counters (counters which counting modulus could be changed dynamically by changing the binary number N given to their parallel load inputs. The described methods for reducing the counting modulus of digital counters are also applicable to binary-decimal counters. The only specific is that the counting number must be presented in binary-coded decimal (BCD), not in binary code. DIGITAL ELECTRONICS