1. EET 1131 Unit 11 Counter Circuits  Read Kleitz, Chapter 12, skipping Sections 12-10 and 12-11.  Homework #11 and Lab #11 due next week.  Quiz next week.

2. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved As you know, the binary count sequence follows a familiar pattern of 0’s and 1’s as described in Section 2-2 of the text. LSB changes on every number. The next bit changes on every other number. 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 The next bit changes on every fourth number. Counting in Binary

3. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved A counter can form the same pattern of 0’s and 1’s with logic levels. The first stage in the counter represents the least significant bit – notice that these waveforms follow the same pattern as counting in binary. LSB MSB Counting in Binary

4. Synchronous versus Asynchronous  The synchronous/asynchronous distinction has different meanings: 1. As applied to inputs: A change on a synchronous input doesn’t affect the outputs until the next active clock edge, but a change on an asynchronous input affects the outputs immediately. 2. As applied to counters: in a synchronous counter, the outputs can all change at the same instant; but in an asynchronous counter, there’s a brief delay between the changing of the outputs.

5. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved In an asynchronous counter, the clock is applied only to the first stage. Each subsequent stage gets its clock from the previous stage. Three bit Asynchronous Counter The asynchronous counter shown is a three-bit counter (also called MOD-8 counter or divide-by-8 counter). It uses J-K flip- flops in the toggle mode. CLK K0K0 J0J0 Q0Q0 Q0Q0 CCC J1J1 J2J2 K1K1 K2K2 Q1Q1 Q2Q2 Q1Q1 HIGH Waveforms are on the following slide…

6. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Three bit Asynchronous Counter CLK Q0Q0 Q1Q1 Q2Q2 Notice that the Q 0 output is triggered on the rising edge of the clock signal. The following stage is triggered from Q 0. The rising edge of Q 0 is equivalent to the falling edge of Q 0. The resulting sequence is that of a 3-bit binary up counter.

7. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Propagation Delay Asynchronous counters are sometimes called ripple counters, because the stages do not all change together. For certain applications requiring high clock rates, this is a major disadvantage. Notice how delays are cumulative as each stage in a counter is clocked later than the previous stage. CLK Q0Q0 Q1Q1 Q2Q2 Q 0 is delayed by 1 propagation delay, Q 1 by 2 delays and Q 2 by 3 delays.

8. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved The 74LS93 Asynchronous Counter The 74LS93 has one independent toggle J-K flip-flop driven by CLK A and three toggle J-K flip-flops that form an asynchronous counter driven by CLK B. CLK A K0K0 J0J0 Q0Q0 CCC J1J1 J2J2 K1K1 K2K2 Q1Q1 Q2Q2 C J3J3 K3K3 Q3Q3 CLK B The counter can be extended to form a 4-bit counter by connecting Q 0 to the CLK B input. Two inputs are provided that clear the count. RO (1) RO (2) All J and K inputs are connected internally HIGH

9. Some Asynchronous Counter ICs  7490 Four bit decade counter (MOD 10) 7490  7492 Four bit divide-by-12 counter (MOD 12)  7493 Four bit binary counter (MOD 16)

10. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Asynchronous Decade Counter This counter uses a NAND gate to recycle the count sequence to zero after the 1001 state, resulting in a MOD-10 counter (or decade counter). Other truncated sequences can be obtained using a similar technique. Waveforms are on the following slide… CLK K0K0 J0J0 Q0Q0 CCC J1J1 J2J2 K1K1 K2K2 Q1Q1 Q2Q2 HIGH C J3J3 K3K3 Q3Q3 CLR

11. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Asynchronous Decade Counter When Q 1 and Q 3 are HIGH together, the counter is cleared by a “glitch” on the CLR line. CLK Q0Q0 Q1Q1 Q2Q2 Q3Q3 CLR Glitch

12. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved BCD Decoder/Driver A special-purpose decoder is the 7447. This is a BCD-to- seven segment display with active LOW outputs. The a-g outputs are designed for much higher current than most devices (hence the word driver in the name). BCD inputs Outputs to seven segment device GND V CC BCD/7-seg BI/RBO LT RBI LT RBI 74LS47

13. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved BCD Decoder/Driver Here the 7447 is an connected to an LED seven segment display. Notice the current-limiting resistors, required to prevent overdriving the LED display.

14. 7447 BCD-to-7-Segment Decoder/Driver  4 input pins for BCD code.  7 output pins to control the seven segments of a 7-segement display.  Also has a lamp test input.  Also a ripple-blanking input and output to suppress leading or trailing zeroes.  Data sheet: 74477447

15. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Synchronous Counters In a synchronous counter all flip-flops are clocked together with a common clock pulse. Synchronous counters overcome the disadvantage of accumulated propagation delays, but generally they require more circuitry to control states changes. K0K0 J0J0 Q0Q0 CCC J1J1 J2J2 K1K1 K2K2 Q0Q1Q0Q1 Q0Q0 Q1Q1 Q2Q2 CLK HIGH This 3-bit binary synchronous counter has the same count sequence as the 3-bit asynchronous counter shown previously.

16. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved A 4-bit Synchronous Binary Counter The 74LS163 is a 4-bit IC synchronous counter with additional features over a basic counter. It has parallel load, a CLR input, two count enables, and a ripple count output that signals when the count has reached the terminal count. Example waveforms are on the next slide… Data inputs Data outputs CLR LOAD ENT ENP CLK RCO Q0Q0 Q1Q1 Q2Q2 Q3Q3 D0D0 D1D1 D2D2 D3D3

17. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Data inputs Data outputs CLR LOAD ENT ENP CLK RCO Q0Q0 Q1Q1 Q2Q2 Q3Q3 D0D0 D1D1 D2D2 D3D3 Clear Preset Count Inhibit 12 13 14 15 0 1 2

18. Some Synchronous Counter ICs  74160 and 74162: Four-bit synchronous decade counters (MOD 10) 74160 and 74162  74161 and 74163: Four bit synchronous binary counters (MOD 16)

19. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Up/Down Synchronous Counters The 74HC191 has the same inputs and outputs but is a synchronous up/down binary (MOD-16) counter. Data inputs Data outputs MAX/MIN CLK Q0Q0 Q1Q1 Q2Q2 Q3Q3 LOAD CTEN RCO D/U D0D0 D1D1 D2D2 D3D3 C CTR DIV 10 74HC190 Data inputs Data outputs MAX/MIN CLK Q0Q0 Q1Q1 Q2Q2 Q3Q3 LOAD CTEN RCO D/U D0D0 D1D1 D2D2 D3D3 C CTR DIV 16 74HC191 The 74HC190 is a high speed CMOS synchronous up/down decade (MOD-10) counter with parallel load capability. It also has a active LOW ripple clock output (RCO) and a MAX/MIN output when the terminal count is reached.

20. Some Up/Down Synchronous Counter ICs  74190 Four bit up/down decade counter (MOD 10) 74190  74191 Four bit up/down binary counter (MOD 16)

21. Cascading Counters  Most counter chips are 4-bit counters, with a modulus of 16 or less.  To get larger moduli, you cascade two or more counter chips together.  When you cascade counters, their moduli multiply, not add. Example: If you cascade a MOD-10 counter with a MOD-16 counter, you get a MOD-160 counter.  The connections for cascading counters differ depending on whether you’re using asynchronous counters or synchronous counters.

22. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Cascaded asynchronous counters

23. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved HIGH CLK Q0Q0 Q1Q1 Q2Q2 C Counter 1 Counter 2 C CTEN CTR DIV 16 Q3Q3 Q0Q0 Q1Q1 Q2Q2 Q3Q3 TC f in a) Each counter divides the frequency by 16. Thus the modulus is 16 2 = 256. For synchronous IC counters, the next counter is enabled only when the terminal count of the previous stage is reached. Cascaded synchronous counters a)What is the modulus of the cascaded DIV 16 counters? b)If f in =100 kHz, what is f out ? f out b) The output frequency is 100 kHz/256 = 391 Hz