1. CHAPTER 6 MODULAR SQUENTIAL CIRCUITS & APPLICATIONS
6-1 Counter
6-2 Register
6-3 Sequence generator
6-4 Digital Clock
Summary

2. 6-1 Counter 1.Categories of counter
Aiming at count the number
of pulse inputted
1.Categories of counter
Clocking way, asynchronous and synchronous
Number of states, modulo-2,10 or arbitrary.
Type of Sequence, up, down and bi-direction.
Scale, SSI and MSI

3. 2.MSI Counter （1）4-Bit Synchronous Binary Counter
（2） 4-Bit Binary Up/Down Counter
（3）MSI Asynchronous Counter

4. （1） 4-Bit Synchronous Binary Counter
1. 4-Bit Synchronous Binary Counter CT74161
2. 4-Bit Synchronous Binary Counter CT74163
3. CT74161/ CT74163 Function Extension

5. (1) Logic Symbol 1. 4-Bit Synchronous Binary Counter CT74161
It consist of 4 master-slave J-K flip-flops.
D  A: highlow
CP: clock pulse，Leading Edge Triggered.
R: Asynchronous Clear, Active-Low.
LD: Synchronous Preset, Active-Low
QD  QA: highlow
P、T：Enable

6. CT74161 Function Table Input Output
CP R LD P(S1) T(S2) A B C D QA QB QC QD
Ф 0 Ф Ф Ф ФФФФ
↑ 1 0 Ф Ф A B C D A B C D
Ф Ф ФФФФ keep unchanged
Ф 1 1 Ф 0 ФФФФ keep unchanged
↑ ФФФФ count

7. (2) Function 1. 4-Bit Synchronous Binary Counter CT74161
1)Asynchronous Clear: if R=0，output will be “0000”, having nothing to do with CP.
2) Synchronous Preset: if R=1 and LD=0，output reflect the data inputs in response to a leading edge of CP.
3)keep: if R=LD=1，all flip-flops will keep unchanged.
4)count: if LD = R = P= T = 1，count in binary system. If the first state is 0000,after 15 CP,the output is “1111”，the ripple clock output (RCO) QCC = TQAQBQCQD =1。After 16th CP, the output return 0000 and QCC = 0.

8. 2. 4-Bit Synchronous Binary Counter CT74163
CT74161 Function Table
CT74163 Function Table
Input Output
CP R LD P(S1) T(S2) A B C D QA QB QC QD
Ф 0 Ф Ф Ф ФФФФ
↑ Ф Ф A B C D A B C D
Ф Ф ФФФФ keep unchanged
Ф 1 1 Ф ФФФФ keep unchanged
↑ ФФФФ Count ↑

9. Characteristics: 2. 4-Bit Synchronous Binary Counter CT74163
(1) Pin arrangement is same as CT74161.
(2) The functions of Preset, Count and Remain are same as CT74161.
(3)The Clear is different from CT74161.
There is an active-LOW clear input, which synchronously reset all four outputs in a positive transition on the CP input.

10. Comparison of 4-Bit Synchronous Binary Counters
CT74161
CT74163
Asynchronous Clear
Synchronous Preset
Remain
Count
Synchronous Clear
Synchronous Preset
Remain
Count

11. (1) Synchronous Preset (2) Feedback Clear (3) Multi-Preset
3. CT74161/ CT74163 Function Extension
connected to achieve arbitrary modulo counter
(1) Synchronous Preset
(2) Feedback Clear
(3) Multi-Preset

12. Example 1: design a modulo-10 counter
(1) Synchronous Preset
Example 1: design a modulo-10 counter
Solution 1: with counting sequence 6,7,…,15
Binary State Sequence
count output
N QD QC QB QA 1 1
QCC=1

13. (1) Synchronous Preset Example 1: design a modulo-10 counter
Binary State Sequence
Count Output
N QD QC QB QA
Solution 2: with counting sequence 0,1,…,9 1
Simulation

14. Example 3: : design a modulo-24 counter using Synchronous Preset
（24）10=（11000）2
2 chips
Initial state:
Last state: 1 1 1

15. (1) Synchronous Preset (2) Feedback Clear (3) Multi-Preset
3. CT74161/ CT74163功能扩展
connected to achieve arbitrary modulo counter
(1) Synchronous Preset
(2) Feedback Clear
(3) Multi-Preset

16. using CT74161 （2）Feedback Clear Binary State Sequence
N QD QC QB QA
Example 1: Function Analysis of The Following Circuits 1

17. （2）Feedback Clear Using CT74161 Binary State Sequence
N QD QC QB QA
Example 2: design a modulo-9 counter

18. （2）Feedback Clear Using CT74163 Example 3: design a modulo-13 counter
Binary State Sequence
N QD QC QB QA
Example 3: design a modulo-13 counter
Simulation

19. (1) Synchronous Preset (2) Feedback Clear (3) Multi-Preset
3. CT74161/ CT74163功能扩展
connected to achieve arbitrary modulo counter
(1) Synchronous Preset
(2) Feedback Clear
(3) Multi-Preset

20. (3) Multi-Preset a modulo-10 counter
Example : Function Analysis of The Following Circuits
Binary State Sequence
N QD QC QB QA 1 1
a modulo-10 counter

21. 2. MSI Counter (1) 4-Bit Synchronous Binary Counter
（2） 4-Bit Binary Up/Down Counter
（3）MSI Asynchronous Counter

22. (2) 4-Bit Binary Up/Down Counter CT74193
Input Output
CPU CPD R LD A B C D QA QB QC QD
φ φ 1 φ φ φ φ φ
φ φ A B C D A B C D
↑ φ φ φ φ up counting
1 ↑ φ φ φ φ down counting
φ φ φ φ remain
CT74193 Function Table

23. (2) 4-Bit Binary Up/Down Counter CT74193
D  A:HIGHLOW
CPU 、CPD :dual clock input
R: asynchronous clear,
active-HIGH.
LD: asynchronous preset,
active-LOW.
QD  QA:HIGHLOW
1. Logic Symbol
QCC=0 in last state
QCB=0 in the first state

24. (1) achieve M<16 counter
(2) 4-Bit Binary Up/Down Counter CT74193
2. CT74193 Function Extension
—— connected to achieve arbitrary modulo counter
(1) achieve M<16 counter
(2) achieve M>16 counter

25. （1） achieve M<16 counter
Method 1: adopt asynchronous preset and up count.
Example: design a modulo-9 counter using CT74193
Binary State Sequence
N QD QC QB QA 1 1
QCC=0

26. （1） achieve M<16 counter
Method 2: adopt asynchronous preset and down count.
（1） achieve M<16 counter
Example: design a modulo-9 counter using CT74193
Binary State Sequence
N QDQCQBQA 1 1
QCB=0

27. (1) achieve M<16 counter
(2) 4-Bit Binary Up/Down Counter CT74193
2. CT74193 Function Extension
—— connected to achieve arbitrary modulo counter
(1) achieve M<16 counter
(2) achieve M>16 counter

28. （2） achieve M > 16 counter
Example: design a modulo-147 counter using CT74193
Method 1: adopt asynchronous preset and up count. 1 1
M = (147)10
=( )2
Need 2 chips of CT74193

29. （2） achieve M > 16 counter
Example: design a modulo-147 counter by using CT74193
Method 2: adopt asynchronous preset and down count, take advantage of QCB 1 1 1 1
M = (147)10
=( )2

30. 2. MSI Counter （1） 4-Bit Synchronous Binary Counter
（2） 4-Bit Binary Up/Down Counter
（3）MSI Asynchronous Counter

31. （3） Asynchronous Counter CT74290
Input Output
CP R0（1）R0（2）Sg（1）Sg（2） QA QB QC QD
Φ Φ Φ
Φ Φ
↓ Φ Φ Count
Φ Φ
Φ Φ
Φ Φ

32. （2） Asynchronous Counter CT74290
(1) Flip-Flop A：M=2 CPA In, QA Out
(2) Flip-Flop B, C, D：M=5 Asynchronous Counter.
CPB In QD  QB Out
CPA、CPB: Clock Input
R01、R02: Clear
Sg1、Sg2 : set 9
QD  QA:HighLow
1 . Logic Symbol

33. （3） Asynchronous Counter CT74290
2. Function
(1) Set 9：if Sg1= Sg2= 1，output is 1001.
If QA is connected with CPB ,
the counter will become an 8421BCD
counter. CPA In QD  QA Out
(2)Asynchronous Clear: if R01=R02=1，one of Sg1, Sg2 is Low，output is “0000”,without regard to CP.
(3)count: if one of R01、R02 and Sg1、Sg2 is Low and CP negative transition appear，the counter will perform.
If QD is connected with CPA ,
the counter will become a 5421BCD
counter. CPB In,QAQD QC QB Out.

34. Example 1: design a modulo-6 counter using CT74290 .
Method 1: take advantage of R
M=6 Binary State Sequence
N QA QB QC QD
0110

35. Example 2: design a modulo-7 counter using CT74290 .
Method 2: take advantage of S
M=7
Binary State Sequence
N QAQBQC QD 1 1

36. Example 3: design a modulo-10 counter using CT74290 .
Requirement: adopt 5421 code
M=10
Binary State Sequence
N QAQDQC QB

37. Example 3: design a modulo-88 counter using CT74290 .
Method 3: 2 chips of CT74290 cascaded 1

38. CHAPTER 6 MODULAR SQUENTIAL CIRCUITS & APPLICATIONS
6-1 Counter
6-2 Register
6-3 Sequence generator
6-4 Digital Clock
Summary

39. Unidirectional Shift Register
1. Category of Register
For storage of data
Register
Shift Register
Unidirectional Shift Register
Bi-directional Shift Register

40. 1.Logic Symbol 2. Register （1）MSI Register CT74175
It is consist of 4 D-Flip-Flops.
2. Function:
Input Output
R CP D Q
０　φ　φ
１　↑　１
１　↑　０
１　０　φ Q Q

41. （1）Shift Register Left Shift Register
Assume flip-flop 4 is the lowest register and flip-flop 1 is the highest register.
According to the characteristic equation of D flip-flop:
When the clock pulse is applied, State of lower flip-flop is shift into the higher as its next state.
Left Shift Register

42. ？ 1 1 1 To load data 1011: Serial Input only One data input line 1
Solution:
Four bits is entered into the register one by one when four clock pulses occurs.
Left Shift Register:
High-first, low-later.
Right Shift Register :
Low-first, high-later
Owe to the circuit is a Left Shift Register, the sequence of data input is 1 1 1

43. To load data 1011，that is D1D2D3D4= 1011CP
Q Q Q Q1 1
1(D1) 2
0(D2) (D1) 3
1(D3) (D2) (D1) 4
1(D4) (D3) (D2) (D1) 1

44. （2）4-bit unidirectional Shift Register CT74195
CT74195 Function Table
Input
Output …… 3
R CP LD SH D J K Q 1 2 3 φ d 1 2 3 1 ↑
0 d0 …… d 3 φ 1 φ Q 00 10 20 30 1 ↑ φ
0 1 Q 0n 1n 2n n 2 1 ↑ φ
0 0
0 Q 0n Q 1n 2n n 2 1 ↑ φ
1 1
1 Q 0n Q 1n 2n n 2 1 ↑ φ
1 0 n Q 0n 1n 2n 2

45. （2）4-bit unidirectional Shift Register CT74195
1.Logic Symbol
2. Function
CT74195
(1) Clear: if R=0，output is “0000”.
(2) Load: if R=1，SH/LD=0, when CP  occurs, parallel load.
(3) Right Shift:if R=1，SH/LD=1， when CP  occurs, right shift.
Q0 is by JK, Q0Q1，
Q1Q2 ，Q2Q3。

46. （3） 4-bit bi-directional Shift Register CT74194
CT74194 Function Table
Input
Output R CP D SR …… D3 MB M A SL Ｑ ０
　　Ｑ
1　　Ｑ
2　　Ｑ3 ０　 φ 　φ
　　φ ０
　　０
１　０ 　φ
　　φ
remain
１　↑ 　φ d …… 3 １ 　１ 1 2 １ Q
１　↑ 　１ 　φ
　　φ 　０ 0n 1n 2n
１　↑ 　０ 　φ
　　φ 　１ Q 0n 1n 2n Q
１　↑ 　φ
　　φ 　１ 　０ 1n 2n 3n １
１　↑ 　φ
　　φ 　１ 　０ Q 1n 2n 3n
１　φ 　φ
　　φ 　０
remain
Note：0—Highest bit … —Lowest bit

47. （3） 4-bit bi-directional Shift Register CT74194
1.Logic Symbol
2. Function
(1) Clear: if R=0，asynchronous clear.
（2）if MA＝MB＝１,parallel load.
（3）if MA＝MB＝０，remain.
（4）if MA=1，MB=0，right shift and data is inputted serially from DSR.
（5）if MA=0 ，MB=1，left shift and data is inputted serially from DSL.

48. 1. Data Conversion 2. Ring Counter 3. Twisted-Ring Counter
（4）Application of Register
1. Data Conversion
2. Ring Counter
3. Twisted-Ring Counter
4. Frequency-Division

49. 1. 7-bit SerialParallel Conversion
ParallelSerial

50. 1. Data Conversion 2. Ring Counter 3. Twisted-Ring Counter
（4）Application of Register
1. Data Conversion
2. Ring Counter
3. Twisted-Ring Counter
4. Frequency-Division

51. 2.Ring Counter
Example: design a M=4 Ring Counter by using CT74195
Binary State Sequence
Ｑ０　　Ｑ１　　Ｑ２　　Ｑ３
１　　　０　　　０　　　０
０　　　１　　　０　　　０
０　　　０　　　１　　　０
０　　　０　　　０　　　１
Notice：
(1) besides effective states, there are still 5 ineffective states.
(2) It has not the ability of self-start. The set-up signal should be applied on SH/Ld to start the loop.

52. Design of Ring Counter （1）How to connect:
The output of shift register Q3 is feedback to the input lines of Ｊ,K.
(2)determine the number of flip-flops:
Modulus of the counter M＝ｎ(n is the number of shift registers.)

53. 1. Data Conversion 2. Ring Counter 3. Twisted-Ring Counter
（4）Application of Register
1. Data Conversion
2. Ring Counter
3. Twisted-Ring Counter
4. Frequency-Division

54. (1) besides effective states, there is still an ineffective states.
Binary State Sequence
Q0 Q Q2 Q3
Example: design a M=8 Twisted-Ring Counter
Notice：
(1) besides effective states, there is still an ineffective states.
(2) It has not the ability of self-start. The set-up pulse signal should be applied on R to clear.

55. Design of Twisted-Ring Counter
（1）How to connect:
The output of shift register Q3 is feedback to the input lines of Ｊ,K via an inverter.
(2)determine the number of flip-flops:
Modulus of the counter M＝2ｎ(n is the number of shift registers.)

56. 1. Data Conversion 2. Ring Counter 3. Twisted-Ring Counter
（4）Application of Register
1. Data Conversion
2. Ring Counter
3. Twisted-Ring Counter
4. Frequency-Division

57. Frequency Divider

58. CHAPTER 6 MODULAR SQUENTIAL CIRCUITS & APPLICATIONS
6-1 Counter
6-2 Register
6-3 Sequence generator
6-4 Digital Clock
Summary

59. 6-3 Sequence generator 1.Counter type Sequence generator
Periodical serial binary code which is arranged by a certain regulation
Arbitrary length sequential code
1.Counter type Sequence generator
2. Feedback type Sequence generator
—maximum-length linear sequence generator

60. 1. Counter type Sequence generator
（1）Circuit Structure
Counter + combinational logic circuits
（2）Design Procedure
1.design modulo-s counter according to the length of sequence. States can be determined freely.
2. Design the combinational Circuits for output data according to the requirement.

61. 1. Counter type Sequence generator
Example: design a Sequence generator which can generate the code
Step 1: design counter
（1）Length of Sequence S=12，therefore a modulo-12 is a preference.
（2）using CT74161
（3）Synchronous preset（4）let effective states are QDQCQBQA=0100～1111. 1

62. 1. Counter type Sequence generator
Step 2: design combinational circuits
（1）write out truth table.
QD QC QB QA Z
(2)Simplification by using K-map
(3) Implement logic function by using 8-input data selector:
D0=D1=D3=D5=0,D2=D6=1
D4=QA，D7=

63. Implement logic function by using 8-input data selector:
The logic variable ABCD
QDQCQB--ABC
QA--D
Select ABC as address input. The K-Map is as follows: AB CD 00 01 11 10 D0 D1 D2 D3 D6 D7 D4 D5
Compared with the K-Map, the data input Di can be determined.
How to determine Di: in the K-Map
If what in the corresponding cells are all 1，Di= 1；otherwise, if what in the corresponding cells are all 0，Di = 0.
If what in the corresponding cells are 0 and 1， Di is SOP of the variables that correspond to 1-cell.

64. 1. Counter type Sequence generator
Step 3: draw the circuit diagram
D0=D1= D3
=D5=0
D2=D6=1
D4=QA，
D7= Z

65. 6-3 Sequence generator 1.Counter type Sequence generator
2. Feedback type Sequence generator
—maximum-length linear sequence generator

66. 1. Length of maximum-length linear sequence：S=2n-1
2. Feedback type maximum-length linear sequence generator (m sequence generator)
1. Length of maximum-length linear sequence：S=2n-1
2. Circuit Structure: shift register + exclusive-OR Gate
(1) According to S=2n-1，determine n.
(2) Look up table 6-31 to find out the feedback function f(Q).
(3) Draw the circuit diagram.
(4) Attach an anti-all-zero logic.
3. Design Procedure:

67. Step 1: S=2n-1，therefore n =3.
2. Feedback type maximum-length linear sequence generator (m sequence generator)
Example : Design an S=7 m sequence generator
Step 1: S=2n-1，therefore n =3.
Step 2: Look up table 6-31 to find out the feedback function：f(Q)=Q2⊕Q3 (即CT74194的DSR= Q1⊕Q2)。
Step 3：draw circuit diagram.

68. 2. Feedback type maximum-length linear sequence generator (m sequence generator)
Example : Design an S=7 m sequence generator
Step 4: add an all-zero correction
Step 5: draw the circuit diagram. By using all-zero state, reload data to implement self-start. The logic diagram is as follows.

69. CHAPTER 6 MODULAR SQUENTIAL CIRCUITS & APPLICATIONS
6-1 Counter
6-2 Register
6-3 Sequence generator
6-4 Digital Clock
Summary

70. Digital Clock is a timing equipment to directly display time by digit, which is consist of crystal oscillator, frequency divider, counter, decoder, display,correction , power supply and so on.
6-4 igital Clock

71. Summary
A few most commonly used modular sequential circuits such as counter, register, shift register and sequence generator are discussed.
Counters can be divided into synchronous and asynchronous; synchronous counters have higher frequency and asynchronous counters have simpler circuits.
Shift registers can be divided into left shift registers, right shift registers and bi-directional shift registers.

72. Objective
（1）familiarize the function table of MSI modular sequential circuits ;
（2）master the function extension of MSI modular sequential circuits ;
（3）have the ability of applying the modular sequential circuits and combinational circuits to fulfill specific logic.

73. Exercises