1. Registers and Counters
Chapter 6

2. Registers and Counters
A register is a group of flip-flops
Each flip-flop stores one bit of info
A counter is a register that goes through a predetermined sequence of binary states

3. Registers 4-bit register with D Flip-flops Common clock input
Common clear input; when Clear=0 flip-flops reset asynchronous

4. Register with parallel load
Exercise: Explain how this register works. Why is it necessary to feed 𝐴 𝑛 back to the combinational input circuit? What if this was not done?

5. Shift Registers
What happens with every clock pulse?

6. Serial transfer

7. Serial addition
Exercise: Describe how you add two binary numbers by hand. How do you apply this to design a serial adder?
Assume you have two n-bit shift registers. Design a circuit that adds one bit at a time and stores the result in one of the shift registers. How do you handle the carries?
Hint: you may need one additional flip-flop.
Indicate the clock connections of the shift registers and the flip-flop.

8. Serial adder

9. Serial adder

10. Serial adder 𝐽 𝑄 =𝑥𝑦 𝐾 𝑄 = 𝑥 ′ 𝑦 ′ =(𝑥+𝑦)′ 𝑆=𝑥⨁𝑦⊕𝑄
𝐾 𝑄 = 𝑥 ′ 𝑦 ′ =(𝑥+𝑦)′
𝑆=𝑥⨁𝑦⊕𝑄
Exercise: Explain how this circuit works. Obtain the excitation/input equations for the JK Flip-flop and the equation for the sum 𝑆.
Run an example sum assuming the circuit uses two 3-bit shift registers.

11. Universal shift register
Clear control to clear register to 0
Clock input to synchronize operations
Shift-right control to enable operation and associated input and output lines
Shift-left control to enable operation and associated input and output lines
Parallel-load control to enable parallel transfer and the n input lines
n parallel output lines
Control state to leave information in the register unchanged

12. Universal shift register
Exercise: explain how this universal shift register works

13. Universal shift register

14. Universal shift register

15. Counters
A counter is a register that goes through a prescribed sequence of states upon the application of input pulses
Two types of counters
Ripple counters
Synchronous counters

16. Ripple Counters 4-bit ripple binary counter with T Flip-flops
Exercise: Obtain the state table.

17. Ripple counters 4-bit binary ripple counter with D flip-flops
Exercise: Explain how this counter works.

18. Ripple Counters

19. State diagram of a decimal BCD counterr
BCD ripple counter
State diagram of a decimal BCD counterr

20. BCD ripple counter
Exercise: Obtain the excitation equation and the state table. Explain how this counter works.

21. Three-decade decimal BCD counter

22. Synchronous Counters Simple design procedure
Least significant digit Flip-flop is complemented with every clock pulse
A flip-flop in any other position is complemented when all the bits in the lower significant positions are equal to 1

23. Synchronous Counters
Exercise: Using the excitation tables for the JK flip-flops explain how this counter works.

24. Up-down binary counter
Countdown binary counter:
Least significant bit is complemented with each clock pulse
A bit in any other position is complemented is all lower significant bits are all equal to 0

25. BCD counter Flip-flop input equations are simplified using maps
𝑇 𝑄1 =1
𝑇 𝑄2 = 𝑄′ 8 𝑄 1
𝑇 𝑄4 = 𝑄 2 𝑄 1
𝑇 𝑄8 = 𝑄 8 𝑄 1 + 𝑄 4 𝑄 2 𝑄 1
𝑦= 𝑄 8 𝑄 1

26. Binary counter with parallel load
Exercise: Explain how this counter works:
When Load is high/low;
When Clear is high/low;
When Count is high/low;
How should Load and Clear be for counting?

27. Binary counter with parallel load

28. BCD counter implemented with counter with parallel load

29. Other Counters
Counter with unused states

30. Other Counters
Counter with unused states

31. Ring counter

32. Johnson counter
Connecting complemented LSB to ring counter input doubles the number of states of ring counter.
What happens if counter starts from an unused state?

33. Homework Assignment
6.4
6.6
6.9 (a)
6.18
6.21
6.23
6.26