Evan Vaughan.  No native support for bit-slicing in Cadence Synthesis Tools ◦ Synopsys does provide this  Trick RTL Compiler and Soc Encounter into.

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Presentation transcript:

Evan Vaughan

 No native support for bit-slicing in Cadence Synthesis Tools ◦ Synopsys does provide this  Trick RTL Compiler and Soc Encounter into laying out and Adder in a bit slice  Use 4 bit Kogge-Stone adder as test design

 Reduce Nangate library to only necessary components ◦ and, or, inv, xor, aoi21  Very disordered layout

 Made no modifications to Nangate library  Want Generate/Propagate blocks to be in order on, on top row

 Synthesized netlist created 4 different instantiations of a half-adder (GPGenerator) and placed them separately  I edited synthesized netlist to have one large instantiation that would be called once.

no change.

 Create a new library using modified Nangate components ◦ Combine four half-adder blocks into one large standard cell ◦ Determine what other components can be combined later  Requires layout and schematic views

 Viewing layouts ◦ Couldn’t directly open.oa layouts in virtuoso ◦ Got around this by “streaming” GDSII layout versions  Schematics ◦ PNG and.edif views  Based schematic off PNG, failed LVS  Couldn’t import.edif  Read through.edif and found that Nangate uses low threshold models  Still failed LVS (no power or ground connections)

 Because just four blocks combined, can just edit.lib and.lef files by hand to create new cells  Shouldn’t be great performance difference between single block and four combined blocks