Status of Integration of Busy Box and D-RORC Csaba Soós ALICE week 3 July 2007.

Slides:



Advertisements
Similar presentations
XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 22 October 2009 Martin Postranecky, Matt Warren, Matthew Wing.
Advertisements

Status of the CTP O.Villalobos Baillie University of Birmingham April 23rd 2009.
Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 DCS – Frontend Monitoring and Control.
DAQ for the TPC Sector Test at Test Beam T10 ALICE DAQ Group ALICE TPC Collaboration Meeting Cagliari, Sardinia 16 – 17 May 2004.
PXL RDO System Requirements And meeting goals 11/12/2009BNL_CD-1_SENSOR_RDO - LG1.
ALICE Trigger System Features Overall layout Central Trigger Processor Local Trigger Unit Software Current status On behalf of ALICE collaboration:D. Evans,
1P. Vande Vyvre - CERN/PH ALICE DAQ Technical Design Report DAQ TDR Task Force Tome ANTICICFranco CARENA Wisla CARENA Ozgur COBANOGLU Ervin DENESRoberto.
11/12 December 20061Borge S. Nielsen, NBI FMD contribution Second Installation and Commissioning Workshop DAQ and ECS FMD contribution Børge S. Nielsen,
Alice EMCAL Meeting, July 2nd EMCAL global trigger status: STU design progress Olivier BOURRION LPSC, Grenoble.
CSCI 4550/8556 Computer Networks Comer, Chapter 10: LAN Wiring, Physical Topology, and Interface Hardware.
Update on DAQ Klaus Schossmaier CERN PH-AID ALICE TPC Meeting 21 April 2006.
6 June 2002UK/HCAL common issues1 Paul Dauncey Imperial College Outline: UK commitments Trigger issues DAQ issues Readout electronics issues Many more.
Readout of TPC with modified ALICE electronics details of current version and pending items ALICE overview New software based on homemade partly existing.
1 Busy logic for the ALICE TPC... Anders Rossebø UiB.
The ALICE TRD - HVDistribution System A. Markouizos, P. Mantzaridis, P. Mitseas, A. Petridis, S. Potirakis, M. Tsilis, M. Vassiliou Athens University ALICE.
1 FEE Installation & Commissioning TPC Meeting, 21 April 2006 L. Musa.
Uli Schäfer 1 JEM1: Status and plans power Jet Sum R S T U VME CC RM ACE CAN Flash TTC JEM1.0 status JEM1.1 Plans.
LP TPC DAQ Ulf Mjörnmark Lund University Present understanding and plan.
ACORDE FOR TPC TEST Status report. Top Modules Bottom Modules.
UNIVERSITY OF BERGEN DEPARTMENT OF PHYSICS 1 UiB DR 2003 High Level API for the TPC-FEE control and configuration.
MSS, ALICE week, 21/9/041 A part of ALICE-DAQ for the Forward Detectors University of Athens Physics Department Annie BELOGIANNI, Paraskevi GANOTI, Filimon.
DDL hardware, DATE training1 Detector Data Link (DDL) DDL hardware Csaba SOOS.
Global Trigger H. Bergauer, K. Kastner, S. Kostner, A. Nentchev, B. Neuherz, N. Neumeister, M. Padrta, P. Porth, H. Rohringer, H. Sakulin, J. Strauss,
Huazhong Normal University (CCNU) Dong Wang.  Introduction to the Scalable Readout System  MRPC Readout Specification  Application of the SRS to CMB-MRPC.
Normal text - click to edit RCU – DCS system in ALICE RCU design, prototyping and test results (TPC & PHOS) Johan Alme.
DPNC Yannick FAVRE Electronics Highlights /12/ Electronics Highlights2 Electronics group  3 Engineers  Daniel La Marra  Stéphane Débieux.
Update on APV25-SRS Electronics Kondo Gnanvo. Outline Various SRS Electronics Status of the APV25-SRS UVa Test of the SRU with multiple.
20/10/2008A. Alici - ALICE TOF Festival1 Electronics and data acquisition of the ALICE TOF detector A.Alici University and INFN, Bologna.
ALICE Rad.Tolerant Electronics, 30 Aug 2004Børge Svane Nielsen, NBI1 FMD – Forward Multiplicity Detector ALICE Meeting on Rad. Tolerant Electronics CERN,
DAQ & ECS for TPC commissioning A few statements about what has been done and what is still in front of us F.Carena.
1 Lecture 7 LAN Wiring, Physical Topology, and Interface Hardware Computer Networks CS 4316.
Local Trigger Unit (LTU) status T. Blažek, V. Černý, M. Kovaľ, R. Lietava Comenius University, Bratislava M. Krivda University of Birmingham 30/08/2012.
ALICE Computing Model The ALICE raw data flow P. VANDE VYVRE – CERN/PH Computing Model WS – 09 Dec CERN.
Bernardo Mota (CERN PH/ED) 17/05/04ALICE TPC Meeting Progress on the RCU Prototyping Bernardo Mota CERN PH/ED Overview Architecture Trigger and Clock Distribution.
The ALICE Forward Multiplicity Detector Kristján Gulbrandsen Niels Bohr Institute for the ALICE Collaboration.
Status report on the development of a readout system based on the SALTRO-16 chip Leif Jönsson Lund University LCTPC Collaboration Meeting
Technical Board Meeting, 14/06/07 Kristján Gulbrandsen, NBI 1 Progress on and Status of the Forward Multiplicity Detector Kristján Gulbrandsen Niels Bohr.
L/O/G/O Input Output Chapter 4 CS.216 Computer Architecture and Organization.
The ALICE Central Trigger Processor (CTP) Upgrade Marian Krivda 1) and Jan Pospíšil 2) On behalf of ALICE collaboration 1) University of Birmingham, Birmingham,
LHCb front-end electronics and its interface to the DAQ.
Costas Foudas, The Tracker Interface to TCS, The CMS Silicon Tracker FED Crates What goes in the FED Crates ? What do we do about the VME controller.
Bart Hommels (for Matthew Wing) EUDET ext. steering board JRA3 DAQ System DAQ System Availability updates: – DIF: Detector Interface – LDA:
17/1/07 F. Formenti PH-ED1 Competence domain (PH-ED) What field of expertise ED can provide?  System electronics design  1.Front-end detector electronics.
Status of TRD Pre-trigger System K. Oyama, T. Krawutschke, A. Rausch, J. Stachel, P. von Walter, R. Schicker and M. Stockmeier for the T0, V0, and TRD.
09/01/2016James Leaver SLINK Current Progress. 09/01/2016James Leaver Hardware Setup Slink Receiver Generic PCI Card Slink Transmitter Transition Card.
The BoNuS Detector Concept Design Status Howard Fenker March 11, 2005.
26/11/02CROP meeting-Nicolas Dumont Dayot 1 CROP (Crate Read Out Processor)  Specifications.  Topology.  Error detection-correction.  Treatment (ECAL/HCAL.
Links from experiments to DAQ systems Jorgen Christiansen PH-ESE 1.
The Past... DDL in ALICE DAQ The DDL project ( )  Collaboration of CERN, Wigner RCP, and Cerntech Ltd.  The major Hungarian engineering contribution.
Peter LICHARD CERN (NA62)1 NA62 Straw tracker electronics Study of different readout schemes Readout electronics frontend backend Plans.
Filippo Costa ALICE DAQ ALICE DAQ future detector readout October 29, 2012 CERN.
ALICE Online Upgrade P. VANDE VYVRE – CERN/PH ALICE meeting in Budapest – March 2012.
ARCHITECTURE. PRR November x 32 PADs Up to 26 or 3 x 17 MANU BOARD. PATCH BUS Translator Board. FEE DETECTOR Up to 100 PATCH BUS per detector. MANU.
TPC electronics Status, Plans, Needs Marcus Larwill April
Vienna Group Discussion Meeting on Luminosity CERN, 9 May 2006 Presented by Claudia-Elisabeth Wulz Luminosity.
A. KlugeFeb 18, 2015 CRU form factor discussion & HLT FPGA processor part II A.Kluge, Feb 18,
1 Carleton/Montreal Electronics development J.-P Martin (Montreal) Shengli Liu & M. Dixit (Carleton) LC TPC Meeting DESY Hamburg, 4 June 2007.
NA 62 TTC partition timing T.Blažek, V.Černý, R.Lietava, M.Kovaľ, M.Krivda Bratislava, Birmingham We are developing procedures for timing parameter adjustment.
COMPUTER NETWORKS CS610 Lecture-11 Hammad Khalid Khan.
1 Timing of the calorimeter monitoring signals 1.Introduction 2.LED trigger signal timing * propagation delay of the broadcast calibration command * calibration.
R. Fantechi 2/09/2014. Milestone table (7/2014) Week 23/6: L0TP/Torino test at least 2 primitive sources, writing to LTU, choke/error test Week.
Integration with ATLAS DAQ Marcin Byszewski 23/11/2011 RD51 Mini week Marcin Byszewski, CERN1.
Sergio Vergara Limon, Guy Fest, September Electronics for High Energy Physics Experiments.
András László KFKI Research Institute for Particle and Nuclear Physics New Read-out System of the NA61 Experiment at CERN SPS Zimányi Winter School ‑ 25.
SVD FADC Status Markus Friedl (HEPHY Vienna) Wetzlar SVD-PXD Meeting, 5 February 2013.
The ALICE Data-Acquisition Read-out Receiver Card C. Soós et al. (for the ALICE collaboration) LECC September 2004, Boston.
TPC Commissioning: DAQ, ECS aspects
ALICE Trigger Upgrade CTP and LTU PRR
L0 processor for NA62 Marian Krivda 1) , Cristina Lazzeroni 1) , Roman Lietava 1)2) 1) University of Birmingham, UK 2) Comenius University, Bratislava,
Commissioning of the ALICE-PHOS trigger
Presentation transcript:

Status of Integration of Busy Box and D-RORC Csaba Soós ALICE week 3 July 2007

2Cs. Soos Introduction The front-end must be able to indicate, when it cannot accept more trigger, in order to avoid overflow in its readout buffers. In the traditional scheme, the front-end generates a BUSY signal, which is connected – either directly, or through the FANIN module – to the LTU. Some sub-detectors (TPC, TRD, PHOS, FMD), due to dense cabling, cannot implement the traditional scheme. The Busy Box concept has been developed in collaboration with the University of Bergen, Norway.

3Cs. Soos Topology DAQ Readout Receiver Card (D-RORC) Front-end Electronics RCU cards DAQ Readout Receiver Card (D-RORC) Front-end Electronics RCU cards DAQ Readout Receiver Card (D-RORC) Front-end Electronics RCU cards DAQ Readout Receiver Card (D-RORC) Front-end Electronics RCU cards DAQ Readout Receiver Card (D-RORC) Front-end Electronics RCU cards Local Trigger Unit (LTU) Busy Box LVDS DDL TTC Busy

4Cs. Soos Data transmission Physical layer LVDS 350 mV on 100 Ω 3.5 mA 2 inputs, 2 outputs (RJ-45 connector) Link layer Asynchronous message (no CLK distribution) 40 Mbps rate Message format (RS232-like) 2 start bits, 16 data bits, 1 parity, 1 stop bit Protocol 1-word request from the Busy Box 3-word reply from the D-RORC The messages shall contain a request ID

5Cs. Soos Request: new ID Communication DCS BBOXD-RORCRCU LTU Sub-event 1 Sub-event 2 Reply: no ID Reply: event ID 1 Request: new ID Compare OK Request: new ID Reply: event ID 2 Compare OK used++ used used++ XOFF Busy TTC Request: new ID Reply: no ID Request: new ID Reply: no ID Request: new ID Reply: no ID

6Cs. Soos Test system in the DDL lab Trigger crate Busy Box TTC BUSY TTC LVDS DDL

7Cs. Soos Test system in the RCU lab Trigger crate Busy Box TTC BUSY TTC LDC + D-RORC DDL LVDS

8Cs. Soos Achievements The communication between the Busy Box and the DRORC has been tested it is reliable, but we should improve to make it more robust The complete chain, including the LTU, DDG as data source, DRORC, and Busy Box has been tested long runs (several hours without interruption) The complete chain, including one RCU (emulating the PHOS readout), DRORC and Busy Box has been tested long runs (4-5 million events) at 1 kHz The complete chain, including 3 RCUs, 3 DRORCs and Busy Box is being tested short runs at 400 Hz problem is being investigated

9Cs. Soos To be done Finish the tests in the RCU lab perform stable runs with 6 RCUs Integrate the Busy Box into the PHOS readout install the Busy Box in the PHOS lab test the system with several RCUs at the highest possible rate Improve communication protocol between the Busy Box and D-RORC the protocol should recover from eventual communication problems Implement the control of the Busy Box at the level of the DCS

10Cs. Soos Thank you

11Cs. Soos Request: new ID

12Cs. Soos Reply: no ID

13Cs. Soos Reply: event ID