1. 1 Busy logic for the ALICE TPC... Anders Rossebø UiB

2. 2 TPC BUSY generation Located in the counting house Standalone PCB (19” rack mount) Input –TTC »L0, L1, L1 message »L2r and L2a message »Clock –D-RORCs »216 End-of-Transfer (EoT) messages »216 Arrival-of-Header (AoH) messages (?) –Ethernet (DCS) Output –BUSY signal to CTP Internal variables –Number of free ALTRO buffers = n_free_buffer –Number of free RCU ping-pong buffers = n_free_pp

3. 3 BUSY control flow Initialization at run start –n_free_buffer = NUMBER_OF_FEC_BUFFERS –n_free_pp = 2 Collision ALIVE L1, L1 message –TPC in trigger maskBUSY L2 message –L2rALIVE –L2a »IF(n_free_buffer > 0) ALIVE »ELSEBUSY »Decrement n_free_buffer & n_free_pp Event fragment header @ LDC –IF((EoT == TRUE).AND. (n_free_pp > 0)) increment n_free_buffer Event fragment has arrived in LDC –ELSE IF(EoT == TRUE) increment n_free_buffer t = 0 t = 5.5  sec t = 100  sec t = 2 msec

4. 4 Busy logic Interfaces Trigger-IF –TTC, BUSY DCS-IF –DIM, TCP/IP, Ethernet RORC-IF –Topology »216 point-to-point connections (STAR topology) – Prototocol »SIMPLEX: unidirectional data transfer (event ID, fragment size), ACK Anders Rossebø, 2006

5. 5 Conceptual design RJ-45 connectors for input and output 2 FPGAs (Xilinx XC4VLX40) DCS board uses Xilinx SelectMAP interface for programming the FPGAs Clock from DCS board JTAG interface Serial communication (LVDS) One ethernet cable for each D-RORC Logic design firmware and ARM-software (C/linux) Implementation (1) Inside the busy box Anders Rossebø, 2006 Ethernet

6. 6 Connection to D-RORC Connectors has same pinout as ethernet Busy logic sends an acknowledge to D-RORC after receiving data TBD in collab. with DAQ Implementation (2) Connection to D-RORC boards Anders Rossebø, 2006 Pair 3 for data to busy logic Pair 2 for acknowledge to D-RORC Cat-5 ethernet cable RJ-45 connector pinout

7. 7 Side view Four extra boards for RJ-45 connectors Extra boards connected to mainboard thru 2 x 96-pin flat cable Implementation (3) 19-inch housing Anders Rossebø, 2006 Front panel Height: 5 U (1 U = 44 mm) Width: 482,6 mm (19”) Depth: 450 mm (TBC)

8. 8 Next steps Soon (Anders will come to CERN on May 3rd) –Detailed specification of hardware/software protocol between DRORC and BUSYBOX - in collaboration with DAQ (Csaba, Wolfgang) –Specification of event fragment message - in collaboration with DAQ (Csaba, Wolfgang) June –First board prototype –Development of firmware/software – in collaboration with DAQ (Csaba, Wolfgang)