Computer Operating Properly Module MTT COMPUTER OPERATING PROPERLY MODULE (COP)

Computer Operating Properly Module MTT Module Objective By the end of this module you should be able to: Understand the COP timer function and purpose Configure the COP for your application needs Module exercise Write a subroutine which will service the COP timer

Computer Operating Properly Module MTT HC08 CPU System Integration Module (SIM) Clock Generation Module (CGM) Timer Interface Module (TIM) Direct Memory Access Module (DMA) Serial Communications Interface (SCI) Internal Bus (IBUS) Serial Peripheral Interface (SPI) Random Access Memory (RAM) Electronically Programmable ROM LVI COP Monitor ROM IRQ BREAK RESET COMPUTER OPERATING PROPERLY (COP) MODULE Watchdog timer system - free running Counter Allows recovery from unexpected events Runaway code Software processing errors

Computer Operating Properly Module MTT COPCTL WRITE CGMXCLK RESET VECTOR FETCH SIM RESET CIRCUIT SIM RESET STATUS REGISTER INTERNAL RESET SOURCES STOP INSTRUCTION SIM 13-BIT SIM COUNTER 6-BIT COP COUNTER COPD (FROM MOR) RESET COPCTL WRITE CLEAR COP MODULE COPEN (FROM SIM) COP COUNTER COP Block Diagram COP Enable - Signal which inhibits COP counter COPRRESET- Generated by SIM from accessing counter IRST - Global Reset, resets COP counter

Computer Operating Properly Module MTT COP Functional Description COP operation Generates an asynchronous reset unless serviced –RST pin held low for 32 CGMXCLK cycles –COP bit in SIM SRS is set to 1 Based on the COP 6 bit counter roll over –Input to the counter is CGMXCLK/8192 Hz –Counter can be disabled preventing COP time out Requires servicing before timeout period With MHz Crystal, COP timeout period is 53.3 ms

Computer Operating Properly Module MTT Refresh rate depends on CGMXCLK frequency COP must be serviced within: Example: 4 MHz external crystal (CGMXCLK = 4 MHz) –COP needs to be serviced within 65.53ms * seconds ~ ~ CGMXCLK frequency 8192 * 32 Seconds COP Reset Rate

Computer Operating Properly Module MTT COP Control Register COP Control register (COPCTL) Overlaps the CPU reset vector Writing any value to COPCTL before counter overflows: –Clears COP counter –Clears bits 12 through 4 of the SIM Counter –Prevents reset –Starts new timeout period Reading COPCTL returns low byte of the reset vector RESET: UNAFFECTED BY RESET D7 D6D5D4 D3 D2D1 D0 COPCTL $FFFF READ: WRITE: Low byte of reset vector Clear COP Counter

Computer Operating Properly Module MTT COP Exercise Write a routine to reset the COP timer.

Computer Operating Properly Module MTT Additional Information - Low Power Modes - Low Power modes WAIT –Operation continues during wait mode ( if enabled ) –To prevent a COP timeout you must periodically clear the COP counter CPU service routine or DMA Service routine STOP –Disables the clock(CGMXCLK) input to the COP module, Clears SIM counter –After exiting Stop, COP counter continues at last value

Computer Operating Properly Module MTT COP Enable/Disable Mask Option Register (MOR) COP Disable (COPD) –Controls COP module –EPROM/OTPROM byte 1 = COP module disabled 0 = COP module enabled (erased state) NOTE: Mask Option Register contents cannot be changed by program Bits set or cleared at time of EPROM/OTP programming RESET: UNAFFECTED BY RESET WRITE: MOR READ: 0 LVISTOP LVIRST LVIPWR SSREC SEC STOP COPD

Computer Operating Properly Module MTT COP Register Summary RESET: UNAFFECTED BY RESET WRITE: MOR READ: 0 LVISTOP LVIRST LVIPWR SSREC SEC STOP COPD RESET: UNAFFECTED BY RESET D7 D6D5D4 D3 D2D1 D0 COPCTL $FFFF READ: WRITE: Low byte of reset vector Clear COP Counter

Computer Operating Properly Module MTT Exercise Solution * COP Module ORG$7000 RSTCOPLDA#$00 STA$FFFF; Reset COP timer RTS