1. The Cortex-M3 Embedded Systems: LM3S9B96 Microcontroller – System Control Refer to Chapter 6 in the reference book “Stellaris® LM3S9B96 Microcontroller - DATA SHEET”

2. High-Level Block Diagram

3. System Control zSystem control configures the overall operation of the device and provides information about the device. zreset control zNMI operation zpower control zclock control zlow-power modes

4. Reset Sources zThe LM3S9B96 microcontroller has six sources of reset zPower-on reset (POR) zThe internal POR circuit monitors the power supply voltage VDD and generates a reset signal to all of the internal logic including JTAG when the power supply ramp reaches a threshold value. zExternal reset input pin (RST) assertion zThe external reset pin (RST) resets the microcontroller including the core and all the on-chip peripherals except the JTAG TAP controller zInternal brown-out (BOR) detector zbrown-out detection circuit that triggers if the power supply VDD drops below a brown-out threshold voltage

5. Reset Sources zSoftware-initiated reset zThe entire microcontroller including the core can be reset by software by setting the SYSRESETREQ bit in the Cortex-M3 Application Interrupt and Reset Control register zOn-chip peripherals can be individually reset by software via three registers (see the SRCRn registers) zA watchdog timer reset condition violation zA watchdog timer can be configured to generate an interrupt to the microcontroller on its first time-out and to generate a reset on its second time-out zMOSC failure zThe LM3S9B96 microcontroller provides a main oscillator verification circuit that generates an error condition if the oscillator is running too fast or two slow

6. z After the processor exits reset, it will read two words from memory: y Address 0x00000000: default value of R13 (MSP) y Address 0x00000004: y If the data at 0x00000004 is not 0xFFFFFFFF, load the Reset vector (the starting address of startup program) y Otherwise, the core executes the ROM Boot Loader Cortex-M3: Reset Sequence

7. Power Control zWithin the MCU, an integrated LDO regulator is used to provide power to the majority of the MCU's internal logic zVoltage output can be programmed zbetween 2.25 V and 2.75 V

8. Clock Control zFundamental Clock Sources zPrecision Internal Oscillator (PIOSC): on-chip clock source, 16MHz + 1%, used by the microcontroller during POR  Main Oscillator (MOSC): an external crystal is connected across the OSC0 input and OSC1 output pins; if PLL is being used, crystal frequency range from 3.579545 MHz to 16.384 MHz (inclusive); if not, between 1 MHz and 16.384 MHz zInternal 30-kHz Oscillator: on-chip clock source, 30kHz + 50%, used during Deep-Sleep power-saving modes zThe internal system clock can be derived from all above clock sources and the output of PLL and PIOSC divided by four (4MHz + 1%)

9. Clock Configuration The Run-Mode Clock Configuration (RCC) and Run- Mode Clock Configuration 2 (RCC2) registers provide control for the system clock zSource of clocks in sleep and deep-sleep modes zSystem clock derived from PLL or other clock source zEnabling/disabling of oscillators and PLL zClock divisors zCrystal input selection

10. Register 7: Run-Mode Clock Configuration (RCC), offset 0x060

15. Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 when the USERCC2 bit is set, allowing the extended capabilities of the RCC2 register to be used

16. Main Clock Tree

17. Configuration on PLL zThe PLL is configured using direct register writes to the RCC/RCC2 register zThe steps required to successfully change the PLL-based system clock are:  1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS bit in the RCC register  2. Select the crystal value ( XTAL ) and oscillator source ( OSCSRC ), and clear the PWRDN bit in RCC/RCC2.  3. Select the desired system divider ( SYSDIV ) in RCC/RCC2 and set the USESYSDIV bit in RCC  4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register  5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2

18. System Control zFor power-savings purposes, the RCGCn, SCGCn, and DCGCn registers control the clock gating logic for each peripheral or block in the system while the microcontroller is in Run, Sleep, and Deep- Sleep mode, respectively. zRun mode: the microcontroller actively executes code. The processor and all of the peripherals that are currently enabled by the RCGCn registers operate normally. zSleep mode: (entered by executing a WFI (Wait for Interrupt) instruction), peripherals enabled by the SCGCn (when auto-clock gating is enabled) registers are clocked, but the processor and the memory subsystem are not clocked. zDeep Sleep mode: (entered by first writing the Deep Sleep Enable bit in the NVIC system control register and then executing a WFI instruction), only peripherals enabled by the DCGCn (when auto- clock gating is enabled) registers are clocked.

19. Register 27: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 zEach bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. All functional modules are disabled after reset.

20. Register 30: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 zEach bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. All functional modules are disabled after reset.

21. Register 33: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 zEach bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. All functional modules are disabled after reset.