1. Interrupt
Source:
under

2. What is an interrupt?
An interrupt is the occurrence of an event that causes a temporary suspension of a program while the event is serviced by a section of code known as the interrupt service routine (ISR).
Execution of
main program
code
Execution of
main program code
Resumed execution of
Execution of ISR
Interrupt request
Time

3. Processor’s response to an interrupt
When an interrupt occurs, the following happens:
The current instruction in the main program completes execution.
The content of PC (i.e., the address of the next instruction in the main program) is saved on the stack.
The address of ISR (i.e., Interrupt vector) for the interrupt is loaded into the PC.
Subsequently, the ISR is executed.
After the execution of the ISR is finished, PC is filled with the stack’s top word, which is the address of the next instruction in the main program.
Subsequently, the execution of the main program is resumed.
ISR: Interrupt Service Routine

4. What is a stack?
A stack is a storage mechanism with the first-in-last-out (FILO) or last-in-first-out (LIFO) access scheme.
Source:

5. Five interrupt sources
The 8051 has five interrupt sources:
Two external interrupts:
INT0-bar (port 3 pin 2);
INT1-bar (port 3 pin 3)
Two internal interrupts:
Timer 0 overflow;
Timer 1 overflow
The serial port:
when a byte has been transmitted or when a byte is received

6. Interrupt-related SFRs: IE, SCON, TCON

7. Interrupt-related SFR: IE (Interrupt Enable Register)
An interrupt can be disabled and enabled.
On power-up or reset, all interrupts are disabled.
* To enable interrupts we set the appropriate bits in the interrupt enable SFR.
Symbol
Bit Number
Description EA 7
Enable/disable all interrupts. If this bit is cleared all interrupts are disabled. If it is set each interrupt source is individually enabled or disabled by setting or clearing the appropriate enable bit, as detailed below. -- 6 5 ES 4
Enable/disable serial port interrupts (set to enable, clear to disable).
ET1 3
Enable/disable timer 1 overflow interrupt (set to enable, clear to disable).
EX1 2
Enable/disable external 1 interrupt (set to enable, clear to disable).
ET0 1
Enable/disable timer 0 overflow interrupt (set to enable, clear to disable).
EX0
Enable/disable external 0 interrupt (set to enable, clear to disable).
Instructions for this purpose:
SETB EA SETB ET0
CLR EX1

8. Interrupt-related SFR: TCON (Timer Control Register)
Bit
Symbol
Bit Address
Description 7
TF1
8FH
Timer 1 overflow flag; set by hardware upon overflow, cleared by software. 6
TR1
8EH
Timer 1 run-control bit; manipulated by software - setting starts timer 1, resetting stops timer 1. 5
TF0
8DH
Timer 0 overflow flag; set by hardware upon overflow, cleared by software. 4
TR0
8CH
Timer 0 run-control bit; manipulated by software - setting starts timer 0, resetting stops timer 0. 3
IE1
8BH
ITx controls the triggering condition of external x interrupt, where x = 0 or 1.
= 1: negative-edge triggering;
= 0: low-level triggering.
IEx is the interrupt flag for external x interrupt, where x = 0 or 1.
= 1: An interrupt request is present;
= 0: An interrupt request is absent. 2
IT1
8AH 1
IE0
89H
IT0
88H

9. Interrupt-related SFR: SCON (Serial Control Register)
Bit
Symbol
Address
Description 7
SM0
9FH
serial port mode bit 0 6
SM1
9EH
serial port mode bit 1 5
SM2
9DH
serial port mode bit 2 - will be dealt with at a later date 4
REN
9CH
receiver enable - this bit must be set to receive data 3
TB8
9BH
transmit bit 8 - this is the ninth bit transmitted in the 9-bit UART modes 2
RB8
9AH
receive bit 8 - this is the ninth bit received in the 9-bit UART modes 1 TI
99H
transmit interrupt flag - this bit is set by hardware when an entire byte has been transmitted - it must be cleared by software RI
98H
receive interrupt flag - this bit is set by hardware when an entire byte has been received - it must be cleared by software

10. Interrupt Flags The 1st bit of TCON register Interrupt Flag Location
External 0
IE0
TCON.1
External 1
IE1
TCON.3
Timer 0
TF0
TCON.5
Timer 1
TF1
TCON.7
Serial Port Receive RI
SCON.0
Serial Port Transmit TI
SCON.1
The 1st bit of TCON register

11. Interrupt Vectors Interrupt Source Interrupt Flag Interrupt Vector
(Address in code memory)
System reset
RST
0000H
External interrupt 0
IE0
0003H
Timer 0
TF0
000BH
External interrupt 1
IE1
0013H
Timer 1
TF1
001BH
Serial port
RI or TI
0023H
When an interrupt in the 8051 occurs, the vector address, as shown above, is loaded into the PC.

12. Scenario of Interrupting

13. External Interrupts Interrupt pins:
the INT0-bar (P3.2) & INT1-bar (P3.3) pins
Triggering conditions:
a low-level or negative edge on the interrupt pins
Choice of the triggering condition:
the IT0 and IT1 bits (in the TCON register)
The interrupt flags:
IE0 and IE1 (in the TCON register);
0 for low-level triggering, 1 for negative edge triggering
Sampling rate
 The external interrupt pins are sampled (ie; tested) once every machine cycle.
Note: Machine cycle = 1 us for 12 MHz clock rate

14. How to program an interrupt
To do
External Interrupt 0
Set up the interrupt vector
ORG 3
JMP EXT0ISR
Choose the interrupt triggering condition (negative-edge or low-level triggering)
SETB IT ; for edge-triggering
CLR IT ; for level-triggering
Enable the interrupt
SETB EX0
Enable all the interrupts
SETB EA
Program the ISR
EXT0ISR:

RETI