A latch is a temporary storage device that has two stable states (bistable). It is a basic form of memory. The S-R (Set-Reset) latch is the most basic type. It can be constructed from NOR gates or NAND gates. With NOR gates, the latch responds to active-HIGH inputs; with NAND gates, it responds to active-LOW inputs. R S Q Q Q Q S R NOR Active-HIGH Latch NAND Active-LOW Latch

The active-HIGH S-R latch is in a stable (latched) condition when both inputs are LOW. R S Q Assume the latch is initially RESET (Q = 0) and the inputs are at their inactive level (0). To SET the latch (Q = 1), a momentary HIGH signal is applied to the S input while the R remains LOW. Latch initially RESET 1 R S Q 1 Latch initially SET

1 R S Q R S Q To RESET the latch (Q = 0), a momentary HIGH signal is applied to the R input while the S remains LOW. 1

Latches S-R latch

Latches The active-LOW S-R latch is in a stable (latched) condition when both inputs are HIGH. Assume the latch is initially RESET (Q = 0) and the inputs are at their inactive level (1). To SET the latch (Q = 1), a momentary LOW signal is applied to the S input while the R remains HIGH. 1 S Q Latch initially RESET 1 Q 1 R S 1 Q Latch initially SET Q 1 R

Never apply an active set and reset at the same time (invalid). 1 S 1 Q Q 1 R To RESET the latch a momentary LOW is applied to the R input while S is HIGH. 1 S Q Never apply an active set and reset at the same time (invalid). 1 Q R

Latches S-R latch

A gated latch is a variation on the basic latch. Gated latches A gated latch is a variation on the basic latch. The gated latch has an additional input, called enable (EN) that must be HIGH in order for the latch to respond to the S and R inputs. S Q EN Q R

Latches Gated S-R latch

A simple rule for the D latch is: The Gated D latch is an variation of the S-R latch but combines the S and R inputs into a single D input as shown: D Q Q D EN EN Q Q A simple rule for the D latch is: Q follows D when the Enable is active.

The truth table for the D latch summarizes its operation The truth table for the D latch summarizes its operation. If EN is LOW, then there is no change in the output and it is latched.

Edge-Triggered Flip-Flops Edge-triggered S-R flip-flop Waveforms

Edge-Triggered Flip-Flops Edge-triggered S-R flip-flop

Edge-Triggered Flip-Flops Edge-triggered D flip-flop Waveforms

Edge-Triggered Flip-Flops Edge-triggered J-K flip-flop Waveforms

Edge-Triggered Flip-Flops Edge-triggered J-K flip-flop

Master-Slave Flip-Flop A master-slave flip-flop is constructed from two seperate flip-flops. One circuit serves as a master and the other as a slave. The logic diagram of an SR flip-flop is shown in Figure. The master flip-flop is enabled on the positive edge of the clock pulse CP and the slave flip-flop is disabled by the inverter. The information at the external R and S inputs is transmitted to the master flip-flop. When the pulse returns to 0, the master flip-flop is disabled and the slave flip-flop is enabled. The slave flip-flop then goes to the same state as the master flip-flop. Logic diagram of a master-slave flip-flop

 The timing relationship is shown in Figure and is assumed that the flip-flop is in the clear state prior to the occurrence of the clock pulse. The output state of the master-slave flip-flop occurs on the negative transition of the clock pulse. Some master-slave flip-flops change output state on the positive transition of the clock pulse by having an additional inverter between the CP terminal and the input of the master. A master–slave D flip-flop is created by connecting two gated D latches in series, and inverting the enable input to one of them. It is called master–slave because the second latch in the series only changes in response to a change in the first (master) latch. The term pulse-triggered means that data is entered on the rising edge of the clock pulse, but the output does not reflect the change until the falling edge of the clock pulse.

For a positive-edge triggered master–slave D flip-flop, when the clock signal is low (logical 0) the "enable" seen by the first or "master" D latch (the inverted clock signal) is high (logical 1). This allows the "master" latch to store the input value when the clock signal transitions from low to high. As the clock signal goes high (0 to 1) the inverted "enable" of the first latch goes low (1 to 0) and the value seen at the input to the master latch is "locked". Nearly simultaneously, the twice inverted "enable" of the second or "slave" D latch transitions from low to high (0 to 1) with the clock signal. This allows the signal captured at the rising edge of the clock by the now "locked" master latch to pass through the "slave" latch. When the clock signal returns to low (1 to 0), the output of the "slave" latch is "locked", and the value seen at the last rising edge of the clock is held while the "master" latch begins to accept new values in preparation for the next rising clock edge.