1 DLD Lecture 16 More Multiplexers, Encoders and Decoders

2 Overview °Binary decoders Converts an n-bit code to a single active output Can be developed using AND/OR gates Can be used to implement logic circuits. °Binary encoders Converts one of 2 n inputs to an n-bit output Useful for compressing data Can be developed using AND/OR gates °Both encoders and decoders are extensively used in digital systems

3 Multiplexer as combinational modules °Connect input variables to select inputs of multiplexer (n-1 for n variables) °Set data inputs to multiplexer equal to values of function for corresponding assignment of select variables °Using a variable at data inputs reduces size of the multiplexer

4 Implementing a Four- Input Function with a Multiplexer

5 Typical multiplexer uses

6 Decoder A decoder is a logic circuit that accepts a set of inputs that represents a binary number and activates only the output that corresponds to the input number. In other words, a decoder circuit looks at its inputs, determines which binary number is present there, and activates the one output that corresponds to that number ; all other outputs remain inactive °In its general form, a decoder has N input lines to handle N bits and form one to 2 N output lines to indicate the presence of one or more N-bit combinations. The basic binary function An AND gate can be used as the basic decoding element because it produces a HIGH output only when all inputs are HIGH

7 Binary Decoder °Black box with n input lines and 2 n output lines °Only one output is a 1 for any given input °Convert binary information from n input lines to 2 n output lines. °Known as n-to-m-line decoder (m = 2 n ). °May be used to generate the 2 n minterms of n input variables. Binary Decoder n inputs m=2 n outputs

8 Decoder (Uses)

9 2-to-4 Decoder °A 2-to-4 Decoder 2 inputs (A 1, A 0 ) 2 2 = 4 outputs (D 3, D 2, D 1, D 0 )

10 2-to-4 Decoder °A 2-to-4 Decoder 2 inputs (A 1, A 0 ) 2 2 = 4 outputs (D 3, D 2, D 1, D 0 ) Truth Table A1A1 A0A0 D0D0 D1D1 D2D2 D3D

11 2-to-4 Decoder °A 2-to-4 Decoder 2 inputs (A 1, A 0 ) 2 2 = 4 outputs (D 3, D 2, D 1, D 0 ) Truth Table A1A1 A0A0 D0D0 D1D1 D2D2 D3D Src: Mano’s book

12 2-to-4 Decoder with Enable ENA1A1 A0A0 D0D0 D1D1 D2D2 D3D3 0XX Truth Table

13 2-to-4 Decoder with Enable ENA1A1 A0A0 D0D0 D1D1 D2D2 D3D3 0XX Src: Mano’s book Truth Table

14 2-to-4 Binary Decoder °From truth table, circuit for 2x4 decoder is: °Note: Each output is a 2- variable minterm (X'Y', X'Y, XY' or XY) F 0 = X'Y' F 1 = X'Y F 2 = XY' F 3 = XY XY Truth Table: 2-to-4 Decoder X Y F0 F1 F2 F3

15 3-to-8 Binary Decoder F 1 = x'y'z xzy F 0 = x'y'z' F 2 = x'yz' F 3 = x'yz F 5 = xy'z F 4 = xy'z' F 6 = xyz' F 7 = xyz Truth Table: 3-to-8 Decoder X Y F0 F1 F2 F3 F4 F5 F6 F7 Z

16 Parallel Decoders

17 Decoders °Parallel is expensive °Problem extending for larger n °2 n decoders require n-input ANDs: fan-in °Alternative: alternate structure

18 Decoder Expansion

19 Implementing Functions Using Decoders °Any n-variable logic function can be implemented using a single n-to-2 n decoder to generate the minterms OR gate forms the sum. The output lines of the decoder corresponding to the minterms of the function are used as inputs to the or gate. °Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2 n decoder with m OR gates. °Suitable when a circuit has many outputs, and each output function is expressed with few minterms.

20 Implementing Functions Using Decoders °Example: Full adder S(x, y, z) =  (1,2,4,7) C(x, y, z) =  (3,5,6,7) 3-to-8 Decoder S2S1S0S2S1S0 x y z S C °A Boolean function, in sum-of- minterms form, can be implemented using: °a decoder to generate the minterms, and °an OR gate to form the sum. °Any combinational circuit with n inputs and m outputs can be implemented with an n:2 n decoder with m OR gates. °Good when circuit has many outputs, and each function is expressed with few minterms.

21 Decoders: Implementing Functions F 1 = A’B’CD + A’BC’D + ABCD Exercise: What are F 2 and F 3 ?

22 Standard MSI Binary Decoders Example (3-to-8 decoder) (a) Logic circuit. (b) Package pin configuration. (c) Function table.

23 Building a Binary Decoder with NAND Gates Start with a 2-bit decoder Add an enable signal (E) Note: use of NANDs only one 0 active! if E = 0

24 Use two 3 to 8 decoders to make 4 to 16 decoder °Enable can also be active high °In this example, only one decoder can be active at a time. °x, y, z effectively select output line for w °When w=0, the top decoder is enabled and the other is disabled. The bottom decoder outputs are all 0’s, and the top eight outputs generate min-terms 0000 to °When w=1, the enable conditions are reversed. The bottom decoder outputs generate min- terms 1000 to 1111, while the outputs of the top decoder are all 0’s.

25 Decoder Application Decoders are used in many types of applications. One example is in computers for I/O selection Computer must communicate with a variety of external devices called peripherals by sending and/or receiving data through what is known as input/output (I/O) ports Each I/O port has a number, called an address, which uniquely identifies it. When the computer wants to communicate with a particular device, it issues the appropriate address code for the I/O port to which that particular device is connected. The binary port address is decoded and appropriate decoder output is activated to enable the I/O port Binary data are transferred within the computer on a data bus, which is a set of parallel lines

26 Encoders °If the decoder's output code has fewer bits than the input code, the device is usually called an encoder. e.g. 2 n -to-n °The simplest encoder is a 2 n -to-n binary encoder O ne of 2 n inputs = 1 Output is an n-bit binary number n inputs n outputs Binary encoder

Encoding - the opposite of decoding - the conversion of an m- bit input code to a n-bit output code with n  m  2 n such that each valid code word produces a unique output code Circuits that perform encoding are called encoders An encoder has 2 n (or fewer) input lines and n output lines which generate the binary code corresponding to the input values Typically, an encoder converts a code containing exactly one bit that is 1 to a binary code corresponding to the position in which the 1 appears n outputs 2 n inputs 2 n -to-n Encoder Encoders

8-to-3 Encoder Description: 2 3 = 8 inputs, 3 outputs one input =1, others = 0’s Each input generate unique binary code 8-to-3 Encoder D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 A0A1A2A0A1A2

8-to-3 Encoder (truth table) 8-to-3 Encoder D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 A0A1A2A0A1A2 inputsoutputs D7D7 D6D6 D5D5 D4D4 D3D3 D2D2 D1D1 D0D0 A2A2 A1A1 A0A

8-to-3 Encoder (truth table) 8-to-3 Encoder D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 A0A1A2A0A1A inputsoutputs D7D7 D6D6 D5D5 D4D4 D3D3 D2D2 D1D1 D0D0 A2A2 A1A1 A0A

8-to-3 Encoder (truth table) 8-to-3 Encoder D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 A0A1A2A0A1A inputsoutputs D7D7 D6D6 D5D5 D4D4 D3D3 D2D2 D1D1 D0D0 A2A2 A1A1 A0A

8-to-3 Encoder (truth table) 8-to-3 Encoder D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 A0A1A2A0A1A inputsoutputs D7D7 D6D6 D5D5 D4D4 D3D3 D2D2 D1D1 D0D0 A2A2 A1A1 A0A

8-to-3 Encoder (truth table) 8-to-3 Encoder D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 A0A1A2A0A1A inputsoutputs D7D7 D6D6 D5D5 D4D4 D3D3 D2D2 D1D1 D0D0 A2A2 A1A1 A0A

8-to-3 Encoder (equations) 8-to-3 Encoder D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 A0A1A2A0A1A2 inputsoutputs D7D7 D6D6 D5D5 D4D4 D3D3 D2D2 D1D1 D0D0 A2A2 A1A1 A0A Note: This truth table is not complete! Why? Output equations: A 0 = ? A 1 = ? A 2 = ?

8-to-3 Encoder (equations) 8-to-3 Encoder D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 A0A1A2A0A1A2 inputsoutputs D7D7 D6D6 D5D5 D4D4 D3D3 D2D2 D1D1 D0D0 A2A2 A1A1 A0A Output equations: A 0 = D 1 + D 3 + D 5 + D 7 A 1 = ? A 2 = ?

8-to-3 Encoder (equations) 8-to-3 Encoder D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 A0A1A2A0A1A2 inputsoutputs D7D7 D6D6 D5D5 D4D4 D3D3 D2D2 D1D1 D0D0 A2A2 A1A1 A0A Output equations: A 0 = D 1 + D 3 + D 5 + D 7 A 1 = D 2 + D 3 + D 6 + D 7 A 2 = ?

8-to-3 Encoder (equations) 8-to-3 Encoder D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 A0A1A2A0A1A2 inputsoutputs D7D7 D6D6 D5D5 D4D4 D3D3 D2D2 D1D1 D0D0 A2A2 A1A1 A0A Output equations: A 0 = D 1 + D 3 + D 5 + D 7 A 1 = D 2 + D 3 + D 6 + D 7 A 2 = D 4 + D 5 + D 6 + D 7

8-to-3 Encoder (circuit) 8-to-3 Encoder D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 A0A1A2A0A1A2 Output equations: A 0 = D 1 + D 3 + D 5 + D 7 A 1 = D 2 + D 3 + D 6 + D 7 A 2 = D 4 + D 5 + D 6 + D 7 A0A1A2A0A1A2 D1D3D5D7D1D3D5D7 D2D3D6D7D2D3D6D7 D4D5D6D7D4D5D6D7

8-to-3 Encoder (limitations) Output equations: A 0 = D 1 + D 3 + D 5 + D 7 A 1 = D 2 + D 3 + D 6 + D 7 A 2 = D 4 + D 5 + D 6 + D 7 inputsoutputs D7D7 D6D6 D5D5 D4D4 D3D3 D2D2 D1D1 D0D0 A2A2 A1A1 A0A Two Limitations: 1. Two or more inputs = 1 Example: D 3 = D 6 = 1 A 2 A 1 A 0 = All inputs = 0 Same as D 0 =1

Priority Encoder Address the previous two limitations 1.Two or more inputs = 1 Consider the bit with highest priority 2.All inputs = 0 Add another output v to indicate this combination

4-to-2 Priority Encoder Description: 2 2 = 4 inputs, outputs Two or more 1’s take highest priority

4-to-2 Priority Encoder inputsoutputs D3D3 D2D2 D1D1 D0D0 A1A1 A0A0 V 0000XX X011 01XX101 1XXX111 Description: 2 2 = 4 inputs, outputs Two or more 1’s take highest priority This is a condensed truth table! It has only 5 rows instead of 16! Row 3 = 2 combinations Row 4 = 4 combinations Row 5 = 8 combinations

4-to-2 Priority Encoder inputsoutputs D3D3 D2D2 D1D1 D0D0 A1A1 A0A0 V 0000XX X011 01XX101 1XXX111 Description: 2 2 = 4 inputs, outputs Two or more 1’s take highest priority

4-to-2 Priority Encoder inputsoutputs D3D3 D2D2 D1D1 D0D0 A1A1 A0A0 V 0000XX X011 01XX101 1XXX111 Description: 2 2 = 4 inputs, outputs Two or more 1’s take highest priority Equations: A 0 = D 3 + D 1 D 2 ’ A 1 = D 2 + D 3 V= D 0 + D 1 + D 2 + D 3

4-to-2 Priority Encoder inputsoutputs D3D3 D2D2 D1D1 D0D0 A1A1 A0A0 V 0000XX X011 01XX101 1XXX111 Description: 2 2 = 4 inputs, outputs Two or more 1’s take highest priority Equations: A 0 = D 3 + D 1 D 2 ’ A 1 = D 2 + D 3 V= D 0 + D 1 + D 2 + D 3

46 Encoder Application (Monitoring Unit) Action EncoderController Machine Code Machine 1 Machine 2 Machine n Alarm Signal Contoller Response °Encoder identifies the requester and encodes the value °Controller accepts digital inputs.

DeMultiplexer Performs the inverse of the operation of a MUX It has one input line, the input from which is transmitted to one of 2n output lines The output lines are selected based on the select inputs E 1x2 DeMUX S D0D1D0D1

1x4 DeMUX The circuit has an input E, the outputs are given by: D 0 = E, if S 0 S 1 =00 D 0 = S 1 ’S 0 ’ E D 1 = E, if S 0 S 1 =01 D 1 = S 1 ’S 0 E D 2 = E, if S 0 S 1 =10 D 2 = S 1 S 0 ’ E D 3 = E, if S 0 S 1 =11 D 3 = S 1 S 0 E E 1x4 DeMUX S 0 S 1 D0D1D2D3D0D1D2D3

DeMUX/Decoder The circuit diagram of a 1x4 DeMUX resembles a 2x4 Decoder with an Enable input For the decoder, the inputs are A 1 and A 0, and the signal E is the Enable For the DeMUX, the inputs S 1 and S 0 are the select inputs and E is the actual input D0D0 D1D1 D2D2 D3D3 S1S1 S0S0 E

50 Summary °Decoder allows for generation of a single binary output from an input binary code For an n-input binary decoder there are 2 n outputs °Decoders are widely used in storage devices (e.g. memories) °Encoders all for data compression °Priority encoders rank inputs and encode the highest priority input