Sub- Nyquist Sampling System Hardware Implementation System Architecture Group – Shai & Yaron Data Transfer, System Integration and Debug Environment Part B – final presentation

Introduction GOALS Concepts 1 st part short review 2 nd part milestones Difficulties we encountered Creating controlling GUI Summary

Sub Nyquist Sampler Digital board Analog board x(t) A/D MODULE User GUI Reconstruction module Providing communication between the units, I.e. transferring data between FPGAs.

Board block diagram

Expander, CTF and DSP must communicate using the board resources. The communication must be efficient and reliable. The system must have a debug environment for the whole units together and separately. The debug environment must be easy to use and requires a GUI

Sub-Nyquist sampling system architecture assembles 3 FPGAs to one electrical circuit composed from few different logical units. Each FPGA contain 1, or more, of these logical units. Since each unit needs to communicate with the other units, there is a need to implement special units for communicating between FGPAs. Large amount of data needs to be transferred between FPGAs using very limited resources.

The whole communication between the FPGAs and the PCI should work flawless, and so, requires a debug environment for the system, in addition to a debug environment for each FPGA by itself.

Learning the ProcStar board and Its abilities: transferring data between FPGAs using Quartos FIFOs and the board’s BUSes.

Learning the ProcStar board and Its abilities: transferring data between FPGAs using Quartos FIFOs and the board’s BUSes. Transferring DATA between FPGAs on board, using Registers and Mega-FIFOs: DATA transferred through Internal FIFO with different Clock Frequencies on input and output ports. doing so, we learnt to transfer large amount of data (more than 200 bits) over the Main BUS (40 bits only).

Learning the ProcStar board and Its abilities: transferring data between FPGAs using Quartos FIFOs and the board’s BUSes. Transferring DATA between FPGAs on board, using Registers and Mega-FIFOs: DATA transferred through Internal FIFO with different Clock Frequencies on input and output ports. doing so, we learnt to transfer large amount of data (more than 200 bits) over the Main BUS (40 bits only). Implementing our own transition devices, due to non-standard requirements of the logical units.

Building Debug Environment for communication between FPGAs, using a Black Box approach inside FPGA, instead of real Hardware; while keeping the self-debug option infrastructure of each unit (previous architecture group environment).

o Adding the Transfer & Receive modules we build in the previous part of the project.

Building required environment for each unit on its designated FPGA, with all its inputs and outputs. The environment enables us to send/receive data, with a large number of bits, over the 40 bit wide main BUS.

Building Debug Environment for communication between FPGAs, using a Black Box approach inside FPGA, instead of real Hardware; while keeping the self-debug option infrastructure of each unit (previous architecture group environment). o Adding the Transfer & Receive modules we build in the previous part of the project. o Adjusting the controllers to have various debugging capabilities.

Building Debug Environment for communication between FPGAs, using a Black Box approach inside FPGA, instead of real Hardware; while keeping the self-debug option infrastructure of each unit (previous architecture group environment). o Adding the Transfer & Receive modules we build in the previous part of the project. o Adjusting the controllers to have various debugging capabilities. o Adding the CTF-DSP interface.

Testing method + work environment for the Modules

1.Testing method for Communication Modules

Testing DATA Stream BER (bit error rate)- the number of bit errors of Data stream over a communication channel, meaning the number of bits that had been altered due to noise, interference, distortion or bit synchronization errors during the DATA stream transfer. Lower & Higher words equal- Check for differences Higher word incremented, Lower word decremented- Plain increment – Sequential DATA change, problem can be seen by eye Toggle 0x , 0xFFFFFFFF- Checks for bits stuck high or low and Checks for ground bounce issues with the input of the driver Toggle : 0xaaaaaaa, 0x Checks for bits stuck high or low - cross coupling Toggle : 0xCCCCCCCC, 0x Add 0xaaaaaaaa each iteration- test random jitter and the asymmetry of transition times. 1-HOT- Pattern contains the longest string of consecutive zeros with the lowest ones density 0-HOT- Pattern contains the longest string of consecutive zeros with the lowest ones density

C Program to compare between input DATA and output DATA Patterns used for test: Lower & Higher words equal Higher word incremented, Lower word decremented Plain increment Toggle 0x , 0xFFFFFFFF Toggle : 0xaaaaaaa, 0x Toggle : 0xCCCCCCCC, 0x Add 0xaaaaaaaa each iteration

1.Testing method for Communication Modules 2.Creating Sub-Nyquist Communication Modules test GUI

1.Testing method for Communication Modules 2.Creating Sub-Nyquist Communication Modules test GUI 3.Integrating all Debug GUI’s under main Window 4.Creating Complete System GUI 5.2 nd part milestones 5.1 Fixing Mega-FIFO error 5.2 Adding missing Modules to the GUI 5.3 Correct separate Modules Debug GUI’s 5.4 Adding functionality to the – “Entire System” GUI 5.5 Debugging the Entire System (all Modules loaded) using the GUI

1.Fixing Mega-FIFO error 2.Adding missing Modules to the GUI 3.Correct separate Modules Debug GUI’s 4.Adding functionality to the – “Entire System” GUI 5.Debugging the Entire System (all Modules loaded) using the GUI

Integration with the units also requires to add existing unit debug environments for each unit, in addition to the system debug environment. What means that each Module can be watched during the work of the complete system

1.Fixing Mega-FIFO error 2.Adding missing Modules to the GUI 3.Correct separate Modules Debug GUI’s 4.Adding functionality to the – “Entire System” GUI 5.Debugging the Entire System (all Modules loaded) using the GUI

Integrating all Debug GUI’s under main Window

1.Fixing Mega-FIFO error 2.Adding missing Modules to the GUI 3.Correct separate Modules Debug GUI’s 4.Adding functionality to the – “Entire System” GUI 5.Debugging the Entire System (all Modules loaded) using the GUI

1.Learning the system and the needed tools 2.Design and test communication Blocks 3.Integrate communication blocks with Black Box Design 4.Test the communication between modules using Black Boxes 5.Prepare Debug GUI 6.Prepare complete System GUI 7.Integrate complete system designs 8.Debug complete system

1.CTF didn’t compile after numerous attempts  start over 2.Procwizard had a bug in the card  new installation fixed it

Questions?

Backup

Transit unit: Placed in Expander’s FPGA Data_in and Valid bit Received from Expander BB. Data_out, Valid bit out and Last signals are sent to CTF and DSP over the Main BUS

Receiver unit: Placed in DSP and CTF’s FPGAs Data_in, Valid bit in and Last signals are received from the Main BUS Data out is the original data that was sent to CTF and DSP. With its Valid bit, it is ready to enter its required logic

Building Debug Environment for communication between FPGAs, using a Black Box approach inside FPGA, instead of real Hardware; while keeping the self-debug option infrastructure of each unit (previous architecture group environment). o Adding the Transfer & Receive modules we build in the previous part of the project. o Adjusting the controllers to have various debugging capabilities. o Adding the CTF-DSP interface.

Building Debug Environment for communication between FPGAs, using a Black Box approach inside FPGA, instead of real Hardware. Debug the environment with a temporary GUI.

Building Debug Environment for communication between FPGAs, using a Black Box approach inside FPGA, instead of real Hardware. Debug the environment with a temporary GUI. In the process of implementing the required Debug Environment there was a need to implement our own transition devices, due to non-standard requirements of the logical units.