Click to edit Master title style STT-RAM Circuit Design Column Circuitry Simulation (IBM 45nm SOI) Fengbo Ren

Summary  Use floating body device as access transistor won’t degrade effective TMR as long as we perform pre-charge in reading operation.  The bipolar current (due to the floating body) will appear at the beginning of writing operation. It should be not enough to be destructive (12uA/um, last for 80 ps).  Min. cell size can be achieved is 17F 2 (F=0.095 um). For min. cell size, I _W(P->AP) =645 uA, I _W(AP->P) =415 uA. More write current than 65-nm for the same cell size.  Use NMOS-only-MUX results in 15-20% write current degradation.  Still working on how to do reliable short pulse reading. 2

Body contacted (BC) v.s. floating body (FB) device  Choosing device for access transistor –Best available BC device has 2x worse drive strength as compared to FB device, it also has body contact making it really big. –In the interest of area, it is better to use FB device, but FB device has variation on R MOS depending upon V body (can range from V in our design), the following slide will analyze how this will affect the effective TMR. 3

Effective TMR  Some definition –TMR = (R AP -R P )/R P –Effective R P (R P_Eff ) = R P +R MOS1 –Effective R AP (R AP_Eff ) = R AP +R MOS2 –Effective TMR = (R AP_Eff -R P_Eff )/R P_Eff – _BC : body connected case – _FB : floating body case  Best case in reading –V body >> 0 and are same when reading R P and R AP –R P_Eff_FB < R P_Eff_BC, R AP_Eff_FB < R AP_Eff_BC,  Worst case in reading –V body = 0 when reading R P, V body >> 0 when reading R AP –R P_Eff_FB = R P_Eff_BC, R AP_Eff_FB < R AP_Eff_BC 4

Effective TMR when body is floating  Best case improve effective TMR a little bit  Worst case degrade effective TMR by 5-6%  For our reading circuit, BL and SL are always pre-charged to the same voltage level. So, V body should always be the same (somewhere between V DD and V SS ) regardless of MTJ resistance. Therefore, by performing pre-charge, we are always in the best case, which means using FB device won’t degrade TMR in our design. 5

Bipolar Current (FB device)  When g = 0, d = 1, s = 1-> 0, since body is floating (V body >>0), we have bipolar current (I bipolar ).  In our design, this current will be seen at the beginning of writing operation. 6 Bipolar current at the beginning of writing operation I bipolar has a peak of 12 uA/um and last for 80 ps, which should be not enough to accidentally flip MTJs. In our design we have 128 WLs, the peak of I bipolar_total will be around 1.5 mA, a high but short current pulse.

Min. Cell Size  Transistor size: –W = 434 nm –L = 40 nm  Cell size: –0.154 um 2 –17 F 2 ● Feature size: um  From 65 -> 45nm –Metal pitch ● 0.2 -> 0.19 um (M4) ● 0.2 -> 0.14 um (M1) –Transistor pitch (D/S shared) ● 0.5 -> um 0.38 um Note: This is the min. cell size can be achieved without violating design rule.

Cell Size v.s. Write Current  Rp = 700 Ohm, TMR = 125%  Boost up V DDW, V WL –dual V WL (V WL_P, V WL_AP )  Recall 65-nm 8 Cell Size (F 2, F=0.095 um (C1)) Transistor W (um) I WP (uA) I WAP (uA) Cell Size (F2) Transistor W (um) I WP (uA) I WAP (uA)

Using NMOS only in MUX  Mux size W –NMOS: W –PMOS: 2W 9 Using NMOS only in MUX will result in 15-20% write current degradation for P- >AP, 10-15% degradation for AP->P. The main reason causes the degradation is that the V GS of the NMOS that close to V DD will be very low during the write operation (Shown in green in the bottom Fig. ), in which case we need a PMOS. So, simply increasing the size of NMOS won’t help.

Read  Normal X-INV based reading –Monte Carlo, TMR=125%  Still working on how to do reliable short pulse reading. –No positive result yet. 10 Rp (Ω) Read time (ps)60~16080~160120~270