Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 12: Intro to the LC-3 Micro-architecture Spring 2009 W. Rhett Davis NC State University with significant material from Paul Franzon, Bill Allen, & Xun Liu

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 2 Announcements l HW#5 Due Thursday » Lab Attendance Required for Q6 l Project #1 Posted » Due in less than 4 weeks » Print out assignment and bring to class

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 3 Summary of Last Lecture l How would you write a 1 to bit 9 in word 107 of a memory? l What command would you use to load a memory for simulation? Where would you put this command?

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 4 Today’s Lecture l Block-Diagram of the LC3 l LC3 Controller State Machine l Control Signals » Controller » Fetch » Execute

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 5 Preliminaries l What is a micro-architecture? l What’s the point of going to all the trouble to build a micro-controller? Why do we care?

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 6 Microarchitecture l The von Neumann Model » Memory » Processor » Input » Output » Control memory processor control input output

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 7 What Blocks Do We Need? l Instructions: » ADD » AND » NOT » BRx » JMP/RET » JSR » JSRR » LD » ST » LDR » STR » LDI » STI l ALU l Register File l Program Counter l Status Register l Instruction Register l Logic to direct operands to/from ALU l Logic to interface to Memory

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 8 Conventions l Control signals are omitted for simplicity » Makes the diagram easier to read » Usually far fewer control signals than data signals l Wire bundles » A set of nets going from one block to another is represented as » When a set of nets contains signals that go in both directions (both input and output for a block), we use » A set of nets on a shared bus (a bus with multiple drivers) is represented as » If a block only reads or writes one signal on a shared bus, we use

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 9 Simplified LC3 Microarchitecture

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 10 Detail of Memory Bus Memory Bus Lines

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 11 Controller l Maintains the master state-machine for the system l Distributes this state to the rest of the system (not shown)

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 12 Fetch l Maintains the program counter (PC) for the system l Communicates with Memory to make sure instruction is made available to Decode block l Master of the shared Memory bus during the all states but the “Read Memory”, “Write Memory”, and “Indirect Address Read” states. l Receives the next address from the Execute block (if a branch is taken)

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 13 Memory Controller Fetch MemAccess Writeback Decode Execute ALU RegFile IR PSR PC State Decode l Maintains the Register File (R0…R7) for the system l Maintains Instruction Register (IR) and Processor Status Register (PSR) l Receives instruction word from Main Memory l Provides operands to Execute and MemAccess blocks l Receives the value to write-back to the RegFile from the Writeback block l Decodes every instruction and provides control signals to most blocks (not shown)

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 14 Execute l Directs operands from the Decode block to the Arithmetic Logic Unit (ALU) l Sends result to the Writeback block (for storage in Register File), or Fetch block (with the next address on a branch)

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 15 MemAccess l Receives Address to be read/written from Execute block l Receives Data to be written from Decode block l Master of the shared Memory bus during the “Read Memory”, “Write Memory”, and “Indirect Address Read” states. l Provides Data read from Memory to Writeback block Memory Controller Fetch MemAccess Writeback Decode Execute ALU RegFile IR PSR PC State

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 16 Writeback l Decides which value will be written back to the Register file l Receives output of ALU from Execute Block l Receives contents of Memory from MemAccess Block l Sends result to Decode Block for storage in Register File Memory Controller Fetch MemAccess Writeback Decode Execute ALU RegFile IR PSR PC State

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 17 Today’s Lecture l Block-Diagram of the LC3 l LC3 Controller State Machine l Control Signals » Controller » Fetch » Execute

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 18 Simplified State Machine

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 19 Execution of ADD/AND/NOT 1. Fetch Unit loads instruction from memory 2. Decode Unit determines the operands 3. Execute Unit applies operands to ALU 4. Result stored in Register File 5. PC incremented

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 20 Execution of BRx/JMP/RET 1. Fetch 2. Decode 3. Execute computes new PC 4. PC updated

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 21 Execution of JSR/JSRR 1. Fetch 2. Decode 3. Execute computes new PC 4. PC stored in R7 5. PC updated

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 22 Execution of LD/LDR 1. Fetch 2. Decode 3. Execute Unit computes address 4. MemAccess Unit reads Memory 5. Write to Register File 6. PC incremented

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 23 Execution of ST/STR 1. Fetch 2. Decode 3. Execute Unit computes address 4. MemAccess Unit writes Memory 5. Update PC

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 24 Execution of LDI 1. Fetch 2. Decode 3. Compute address 4. Read Memory for Indirect Address 5. Read Memory 6. Update Register File 7. PC incremented

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 25 Execution of STI 1. Fetch 2. Decode 3. Compute address 4. Read Memory for Indirect Address 5. Write to Memory 6. Update PC

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 26 Execution of LEA 1. Fetch 2. Decode 3. Compute address 4. Update Register File 5. Update PC

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 27 How Good Is Our Micro-architecture? l What is the average number of cycles per instruction l Modern microprocessors get this number close to 1.0 for scalar machines and less than 1.0 for super-scalar and VLIW machines. l Take courses like ECE 463 & ECE 464 to learn how.

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 28 Today’s Lecture l Block-Diagram of the LC3 l LC3 Controller State Machine l Control Signals » Controller » Fetch » Execute

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 29 Control Signal Tables l It helps greatly in the debugging of the LC-3 System to have completed tables that give the values of various control signals, depending on the instruction that is being executed. l In this section, we will begin to fill out these tables. l The instruction-set specification is needed to complete these tables, and is included here for convenience.

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 30 ALU Operations l ADD l AND l NOT DR SR100 SR2 0 1 DR SR100 SR DR SR11 imm50 1 DR SR11 imm DR SR

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 31 Control Instructions l BR l JMP l JSR l JSRR l RET l RTI l TRAP 0 0 NZP PCoffset BaseR BaseR PCoffset Trapvect8

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 32 Load/Store Instructions l LD: l LDR: l LDI: l LEA: l ST: l STR: l STI: DR BaseR Offset DR PCoffset91 0 DR PCoffset DR PCoffset SR PCoffset SR PCoffset SR BaseR Offset6

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 33 Complete the Table C_Control OperationmodeInstr. TypeStore PCMem. Access Modeload ADD0 1 AND0 1 NOT BR JMP/RET JSR JSRR LD LDR LDI LEA ST STR STI

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 34 Fetch Inputs & Outputs l Input Signals: » clock – global system clock. » reset – when high, the PC should be synchronously set to x3000 » state – the state from the Controller block. » taddr[15:0] – the next value of the PC if a branch is taken. » br_taken – signal to indicate that a branch is taken. l Output Signals: » rd – signal to indicate to the Memory that a read is to be performed, rather than a write. This signals should be high- impedence during the “Read Memory”, “Write Memory”, and “Indirect Address Read” states, because the MemAccess block will drive the shared bus during these cycles. In all other states, this signal should be high. » pc – the current value of the program counter, but should be high-impedence at the same times that the rd signal is high- impedence. » npc – should always be PC+1.

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 35 Fetch Block Sketch

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 36 Complete the Table Operationmodebr_taken ADD0 1 AND0 1 NOT BR JMP/RET JSR JSRR LD LDR LDI LEA ST STR STI

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 37 Execute Block Sketch

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 38 Complete the Table E_Control OperationmodeALU Op SelPC Sel 1PC Sel 2OP 2 Sel ADD0 1 AND0 1 NOT BR JMP/RET JSR JSRR LD LDR LDI LEA ST STR STI