1. Chapter 5 The LC-3 LC-3 Computer Architecture Memory Map
Instruction Set Architecture (ISA)
Machine Instructions
Address Modes
Instructions
- Operate
- Data Move
- Control
Programming in Machine Code

2. The LC-3 Computer a von Neumann machine
The Instruction Cycle:
Fetch: Next Instruction from Memory
(PC)  (points to) next instruction
PC (PC) + 1
Decode: Fetched Instruction
Evaluate: Instr & Address (es)
(find where the data is)
Load: Operand (s)
(get data as specified)
Execute: Operation
Store: Result
(if specified)
PSW
Memory
PSW (Program Status Word):
Bits:
| S| |Priority| | N| Z| P|

3. Important Registers in the CPU
8 General Purpose Registers (R0 – R7) – Holds Data or Addresses
Program Counter (PC) - Points to the next instruction
Instruction Register (IR) – holds the instruction being executed
Memory Address Register (MAR) – Holds the address of a memory location being accessed
Memory Data Register (MDR) – Hold the data to be written into memory or the date read from memory
Program Status Word (PSW) – holds the status of the program being executed, including N Z P: Negative, Zero, Positive result of an operate instruction
Note: These are all 16 bit registers

4. LC-3 Memory Map (64K of 16 bit words) 256 words
(We will get to theses today)
(We will get to these later)
23.5 K words
39.5 K words
512 words

5. LC-3 Instructions (Fig 5.3 & Appendix a)
Addressing Modes
Register
(Operand is in one of the 8 registers)
PC-relative
(Operand is “offset” from where the PC points
- offsets are sign extended to 16 bits)
Base + Offset (Base relative)
(Operand is “offset” from the contents of a register)
Immediate
(Operand is in the instruction)
Indirect
(The “Operand” points to the real address of Operand
– rather than being the operand)
Note: The LC-3 has No Direct Addressing Mode

6. Operate Instructions - ADD Register mode [0001 DR SR1 0 00 SR2]
There are only three operate Instructions:
- ADD Register mode [0001 DR SR SR2]
Register/Immediate mode [0001 DR SR1 1 imm5]
- AND Register mode [0101 DR SR SR2]
Register/Immediate mode [0101 DR SR1 1 imm5]
- NOT Register mode [1001 DR SR ]
The Source and Destination operands are:
CPU Registers or Immediate Values

7. LC-3 Instructions (Fig 5.3 & Appendix a)
Addressing Modes
Register
(Operand is in one of the 8 registers)
PC-relative
(Operand is “offset” from where the PC points
- offsets are sign extended to 16 bits)
Base + Offset (Base relative)
(Operand is “offset” from the contents of a register)
Immediate
(Operand is in the instruction)
Indirect
(The “Operand” points to the real address of Operand
– rather than being the operand)
Note: The LC-3 has No Direct Addressing Mode

8. Data Movement Instructions
Load - read data from memory to a register
LD: PC-relative mode [0010 DR PCoffset9]
LDI: Indirect mode [1010 DR PCoffset9]
LDR: Base+offset mode [0110 DR BaseR offset6]
Store - write data from a register to memory
ST: PC-relative mode [0011 DR PCoffset9]
STI: Indirect mode [1011 DR PCoffset9]
STR: Base+offset mode [0111 DR BaseR offset6]
Load effective address – address saved in register
LEA: PC-relative mode [1110 DR PCoffset9]

9. LC-3 Instructions (Fig 5.3 & Appendix a)
Addressing Modes
Register
(Operand is in one of the 8 registers)
PC-relative
(Operand is “offset” from where the PC points
- offsets are sign extended to 16 bits)
Base + Offset (Base relative)
(Operand is “offset” from the contents of a register)
Immediate
(Operand is in the instruction)
Indirect
(The “Operand” points to the real address of Operand
– rather than being the operand)
Note: The LC-3 has No Direct Addressing Mode

10. Go to New Location in Program – “GO TO”
Control Instructions
Go to New Location in Program – “GO TO”
BR: PC-relative mode [0000 NZP PCoffset9]
JMP: Indirect mode [ BaseR ]
Trap Service Routine Call
TRAP: Indirect [ TrapVec8]
Jump to Subroutine (will be covered later)
JSR: PC-relative mode [ PCoffset11]
JSRR: Indirect mode [ BaseR ]
Return from Trap/Subroutine
RET: No operand [ ]
Return from Interrupt (will be covered later)
RTI: No operand [ ]

11. LC-3 Instructions (Fig 5.3 & Appendix a)
Addressing Modes
Register
(Operand is in one of the 8 registers)
PC-relative
(Operand is “offset” from where the PC points
- offsets are sign extended to 16 bits)
Base + Offset (Base relative)
(Operand is “offset” from the contents of a register)
Immediate
(Operand is in the instruction)
Indirect
(The “Operand” points to the real address of Operand
– rather than being the operand)
Note: The LC-3 has No Direct Addressing Mode

12. Branch Instruction BR [0000 nzp PCoffset9]
Branch specifies one or more condition codes
Program Status Word (PSW):
Bits:
| S| |Priority| |N|Z|P|
If the specified bit(s) is (are) set, the branch is taken:
PC is set to the address specified in the instruction
Target (new PC) address is computed by:
adding SEXT(IR[8:0]) to the PC contents
If the branch is not taken: - the next sequential instruction is executed (presently pointed to by the PC).

13. BR +
If all zero, no CC is tested, so branch is never taken. (See Appendix B.)
If all one, then all are tested. Since at least one of the CC bits is set to one after each operate/load instruction, then branch is always taken. (Assumes some instruction has set CC before branch instruction, otherwise undefined.)
SEXT

14. Jump Instruction JMP BaseR [1100 000 BaseR 000000]
Jump is an unconditional branch -- always taken.
BaseR
New PC contents (an Address) is the contents of the Base register
Allows any target address !

15. Example LC-3 Program
Write a program to add 12 integers and store the result in a Register.

16. Compute the Sum of 12 Integers Program
Program begins at location x3000.
Integers begin at location x3100.
R1  x3100 R3  0 (Sum) R2  12(count)
R2=0?
R4  M[R1] R3  R3+R4 R1  R1+1
R2  R2-1 NO
YES
R1: “Array” index pointer (Begin with location 3100)
R3: Accumulator for the sum of integers
R2: Loop counter (Count down from 12)
R4: Temporary register to store next integer

17. Sum integers from x3100 – x310B What happens at location 300A ?
Address
Instruction
Comments
x3000
R1  x3100
x3001
R3  0
x3002
R2  0
x3003
R2  12
x3004
If Z, goto x300A
x3005
Load next value to R4
x3006
Add to R3
x3007
Increment R1 (pointer)
X3008
Decrement R2 (counter)
x3009
Goto x3004
R1: “Array” index pointer (Begin with location 3100) R3: Accumulator for the sum of integers
R2: Loop counter (Count down from 12) R4: Temporary register to store next integer
What happens at location 300A ?

18. LC-3 Instructions (Fig 5.3 & Appendix a)
Addressing Modes
Register
(Operand is in one of the 8 registers)
PC-relative
(Operand is “offset” from where the PC points
- offsets are sign extended to 16 bits)
Base + Offset (Base relative)
(Operand is “offset” from the contents of a register)
Immediate
(Operand is in the instruction)
Indirect
(The “Operand” points to the real address of Operand
– rather than being the operand)
Note: The LC-3 has No Direct Addressing Mode

19. The Sum program in “binary”
x ;R1=x3100
x ;R3=0
x ;R2=0
x ;R2=R2+12
x ;If z goto x300A
x ;Load next value into R4
x ;R3=R3+R4
x ;R1=R1+1
x ;R2=R2-1
x ;goto x3004
x300A ;halt

20. The Sum program in “hex”
x E2FF ;R1=x3100
x E0 ;R3=0
x A0 ;R2=0
x AC ;R2=R2+12
x ;If z goto x300A
x ;Load next value into R4
x C4 ;R3=R3+R4
x ;R1=R1+1
x BF ;R2=R2-1
x FFA ;goto x3004
x300A F025 ;halt

21. The Sum program Data in “hex”
x ; Loc x3100 x x x
x FFFF
x C10
x B1 x
x F07 x
x310A 0A00
x310B 400F ; Loc x310B

22. TRAP Instruction RET [1100 000 111 000000]
Calls a service routine, identified by 8-bit “trap vector.”
Register R7 is loaded with the incremented contents of the PC.
The PC is loaded with the address in the Trapvector Table at position “trapvector8”
R0 is typically used for passing values between the Program and the Trap Routine
RET [ ]
When service routine is done, an RET will load R7 (the incremented value of the PC before jumping to the TRAP routine) into the PC, and the program will continue with the next instruction after the TRAP, i.e. the program will “return” from the TRAP Routine.
Note: an RET is a JMP Base-relative with Base = R7
vector
Service routine (Partial List)
x23
input a character from the keyboard
x21
output a character to the monitor
x25
halt the program

23. TRAPS
See page 543.