1. Introduction to Computing Systems from bits & gates to C & beyond Chapter 5 The LC-2 Instruction Set Architecture Operate instructions Data Movement instructions Control Instructions

2. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 2 ISA Overview Memory  Address space  Addressability: Word or Byte Registers  Number  Type Instructions  Operations  Data Types  Addressing Modes

3. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 3 LC-2 Memory Organization addressability word (16 bits/location) address space 2 16 locations = 64k 2 9 words/page = 512 2 7 pages =128 pagelocation in page [8:0] [15:9] Address [16:0]

4. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 4 General Purpose Registers (GPRs) Registers  Special “memory” that is “inside” the CPU  Very fast access: 1 clock cycle.  General Purpose Registers: addressable by an instrcution (visible to the user).  Other registers may not be accessible (not architectured) LC-2  8 general purpose registers: R0,R1,...,R7  a register can hold any 16 bit pattern - I.e. data or addresses  Other special purpose registers (later)

5. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 5 Instructions Two main parts  Opcode: specifies what the instruction does.  Operand(s): what the instruction acts on  Instruction sets can be complex or simple LC-2  4-bit opcode => 16 instructions  up to two sources and one destination  Example: 0 0 0 10 1 10 0 1 01 0 0 0 0 ADDR3R1R4 15 14 13 1211 10 98 7 6 52 1 0 4 3

6. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 6 Operations Operate  Manipulate data directly  ADD, AND, NOT Data Movement  Move data between memory and registers (CPU)  LD, LDI, LDR, LEA, ST, STI, STR Control  Change the sequence of instruction execution  BR, JMP/JSR, JMPR/JSSR, RET, RTI, TRAP

7. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 7 Data Types What data types are supported by the computer instructions?  Eg. integer, floating point, BCD, character... LC-2: only 2's complement integers  bit strings and addresses are not data types

8. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 8 Condition Codes 3 single-bit registers (set to 1 or cleared to 0)  N: value written was negative  Z: value written was zero  P: value written was positive Affected each time any register is written Condition codes are read by conditional branch instructions

9. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 9 Addressing Modes - 1 Where is the operand?  The addressing modes provide multiple mechanisms for the instruction to specify the location of an operand. Effective Address (EA)  The address that is used to locate the operand. LC-2 supports five addressing modes:  explicitly in the instruction itself (immediate)  in a register  in memory, by specifying  the address of the operand (two modes: direct and base+offset)  the address of a location that contains the address of the operand (indirect)

10. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 10 Immediate & Register Operands Immediate  If bit 5 = 1, the value in [4:0] (“immediate”) is sign extended (SEXT) to 16 bits and added to the contents of the source register SR1 ([8:6]). Register  if bit 5 = 0, the contents of source register SR2 ([2:0]) are added to the contents of source register SR1 ([8:6]).  In both cases, the result goes to the destination register DR ([11:9]). opcodeoperands ADDDRSR11imm [15:12][11:9][8:6][5][4:0] ADDDRSR10 [15:12][11:9][8:6][5][2:0] SR2 opcodeoperands

11. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 11 Memory Addressing Modes Direct addressing  effective address = [instruction page no.]@[page offset]  note that the 9 bit page offset (=> 512 locations) is concatenated with (not added to) the 7 bit page number (=> 128 pages)  operand location must be on the same page as current instruction Indirect addressing  Same mechanism as above, but the calculated memory location now contains the address of the operand, (i.e. the ea is indirect).  Note that the memory has to be accessed twice to get the actual operand. LDDRpage offset [15:12][11:9] [8:0] LDIDRpage offset [15:12][11:9] [8:0]

12. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 12 Memory Addressing Modes - 2 Base+Offset addressing  effective address = (BaseRegister) + offset  zero extend (ZEXT) the 6 bit offset ([5:0]) to 16 bits  add it to the contents of the Base Register ([8:6])  differences from Direct addressing (pageoffset):  base offset is added, page offset is concatenated  base offset range is only 6 bits (=> 64 locations), page offset is 9 bits  base offset can address any location in memory, page offset only in current page LDRDRBaseR [15:12][11:9][8:6] [5:0] offset

13. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 13 Operate Instructions - 1 Arithmetic and Logic  arithmetic: add, subtract, multiply, divide (the LC-2 only has add)  logic: and, or, not, xor (the LC-2 only has and, not) LC-2: ADD, AND & NOT 0 0 0 10 1 10 1 0 01 0 1 0 0 ADDR3R2 dest regsrc reg R5 NOTR3R2 dest regsrc reg 1 0 0 10 1 10 1 0 00 0 0 0 0

14. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 14 Operate Instructions - 2 Not  uses one source [8:6] register and one destination [11:9] register  bits [5:0] are all 1s. ADD & AND  destination register in [11:9], one source register in [8:6]  other source  register operand:  if bit [5] = 0, bits [2:0] specify a register for the other source  immediate operand:  if bit [5] = 1, bits [4:0] specify the other source number directly, as a 5 bit 2’s complement integer, which is sign extended (SEXT) to 16 bits.

15. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 15 ADD: Two's complement 16-bit Addition Assembler Instruction ADD DR, SR1, SR2 ; DR = SR1 + SR2 (register addressing) ADD DR, SR1, imm5 ; DR = SR1 + Sext(imm5) (immediate addressing) Encoding 0001 DR SR1 0 00 SR2 0001 DR SR1 1 imm5 Examples ADD R2,R3,R6 ADD R2,R3,#1  Note: Condition codes are set

16. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 16 AND: Bitwise Logical AND Assembler Instruction AND DR,SR1,SR2 ; DR = SR1 AND SR2 AND DR,SR1,imm5 ; DR = SR1 AND Sext(imm5) Encoding 0101 DR SR1 0 00 SR2 0101 DR SR1 1 imm5 Examples AND R2,R3,R6 AND R2,R2,#0 ; Clear R2 to 0  Note: Condition codes are set.

17. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 17 NOT: Bitwise Logical NOT Assembler Inst. NOT DR,SR ; DR = NOT SR Encoding 1001 DR SR 111111 Example NOT R2,R6  Note: Condition codes are set.

18. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 18 Data Movement Instructions - 1 Move Data  from CPU register to memory => store  nominated register is Source  from memory to register => load  nominated register is Destination  also to/from I/O devices (later) LC-2 Load/Store Instructions  LD, LDI, LDR, LEA, ST, STI, STR  Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 opcode DR or SR operand specifier

19. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 19 Data Movement Instructions - 2 LC-2 Load/Store Instructions  immediate: LEA No Effective Address (EA) calculation; the value (PC[15:9] concatenated with instruction[8:0]) is loaded directly into DR - i.e. DR <= PC[15:9] @ Inst[8:0]  direct: LD & ST The EA is [15:9] from PC, [8:0] from instruction (page-offset mode)- i.e. EA = PC[15:9] @ Inst[8:0] DR <= Mem[PC[15:9] @ Inst[8:0] ]  indirect: LDI & SDI EA = Mem[ PC[15:9] @ Inst[8:0] ] DR <= Mem[Mem[ PC[15:9] @ Inst[8:0] ]  base+offset: LDR & STR (BaseReg is specified by Inst [8:6]) EA = BaseReg + Zext(Inst[5:0]) DR <= Mem[BaseReg + ZEXT(Inst[5:0])]

20. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 20 LD: Load Direct Assembler Inst. LD DR, LABEL ; DR = Mem[LABEL] Encoding 0010 DR page-offset9 Examples LD R2, param Notes: The LABEL must be on the same memory page as the instruction. Condition codes are set.

21. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 21 LDI: Load Indirect Assembler Inst. LDI DR, LABEL ; DR = Mem[Mem[LABEL]] Encoding 1010 DR pgoffset9 Examples LDI R2, POINTER Notes: The LABEL must be on the same memory page as the instruction. Condition codes are set.

22. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 22 LDR: Load Base+Index LDR: Load Base+Index Assembler Inst. LDR DR,BaseR,idx6 ; DR = Mem[BaseR+ZEXT(idx6)] Encoding 0110 DR BaseR index6 Examples LD R2,R3,#15 ; R2 = Mem[R3+15] Notes: The index is zero-extended to 16 bits. Condition codes are set.

23. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 23 LEA: Load Effective Address Assembler Inst. LEA DR, LABEL ; DR = LABEL Encoding 1110 DR pgoffset9 (i.e. address of LABEL = PC[15:9] + pgoffset9) Examples LEA R2, DATA ; R2 gets the address of DATA Notes: The LABEL must be on the same memory page as the instruction. Condition codes are set.

24. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 24 ST: Store Direct ST: Store Direct Assembler Inst. ST SR, LABEL ; Mem[LABEL] = SR Encoding 0011 SR pgoffset9 Examples ST R2, VALUE ; Mem[VALUE] = R2 Notes: The LABEL must be on the same memory page as the instruction. Condition codes are not set.

25. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 25 STI: Store Indirect STI: Store Indirect Assembler Inst. STI SR, LABEL ; Mem[Mem[LABEL]] = SR Encoding 0011 SR pgoffset9 Examples STI R2, POINTER ; Mem[Mem[POINTER]] = R2 Notes: The LABEL must be on the same memory page as the instruction. Condition codes are not set.

26. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 26 STR: Store Base+Index Assembler Inst. STR SR, BaseR,idx6 ; Mem[BaseR+ZEXT(idx6)]=SR Encoding 0111 SR pgoffset9 Examples STR R2, R4, #15 ; Mem[R4+15] = R2 Notes: The index is zero-extended to 16 bits. Condition codes are not set.

27. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 27 Addressing Examples What is the EA for the following instructions? Given: PC = x2081, R6 = x2035, LOC = x2044, Mem[LOC] = x3456 ADD R1,R3,R2 Register addressing: DR = R1, SR1 = R3, SR2 = R2 DR <= ? ADD R5,R1,#15 Immediate addressing: DR = R5, SR1 = R1, S2 = 15 DR <= ? LD R1,LOC Direct addressing: DR <= ? LDI R2,LOC Indirect addressing: EA = Mem[x2044] = x3456 LDR R1,R6,#12 Base+Offset addressing: EA = R6+12 = x2035 + x000C = x2041

28. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 28 Control Instructions Change the Program Counter  Conditionally or not  Remember where it was (subroutine calls) LC-2 Instructions  BRx, JMP/JSR, JMPR/JSRR, RET, TRAP  BRx, JMP, JSR use direct addressing  JMPR, JSRR use base+offset addressing Conditional Branch: BRx 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 page offset N Z P

29. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 29 BR: Conditional Branch BR: Conditional Branch Assembler Inst. BR LABEL BRn LABEL BRz LABEL BRp LABEL BRnz LABEL BRnp LABEL BRzp LABEL BRnzp LABEL Encoding 0000 n z p pgoffset9 Examples BRzp LOOP ; branch to LOOP if previous op returned zero or positive. Note: Branch to LABEL iff the selected condition code(s) is set

30. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 30 TRAP Instruction  Used to invoke an operating system service call  Trap vectors: a list of locations of the service call routines  TRAP has one operand which indexes into the trap vector; PC is set to the value (starting point of service routine)  Some special trap vectors: * x23: input a character from the keyboard * x21: output a character to the monitor * x25: halt the program  More details later

31. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 31 TRAP: Invoke a system routine Assembler Inst. TRAP trapvec Encoding 1111 0000 trapvect8 Examples TRAP x23 Note:R7 <= PC (for eventual return) PC <= mem[Zext(trapvect8)]

32. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 32 Data Path - 1  Global Bus  16-bit  connects all components  is shared by all  Memory  Memory Address Register: MAR  address of location to be accessed  Memory Data Register: MDR  data loaded or to be stored

33. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 33 Data Path - 2  ALU & Registers  Two ALU sources  source 1: register  source 2: register or instruction  Result: goes onto bus, then to DR  PC & PCMUX  PC sends address to MAR for instruction fetch  PCMUX: a 4:1 mux that selects the new PC  incremented PC  BR  TRAP, RET or JSR (later)

34. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 34 Data Path - 3  MARMUX  A 3:1 mux that selects the source of MAR  Right input: direct, indirect addressing  Middle input: base+offset addressing  Left input: trap instruction

35. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 35 Instruction Cycle - 1 Given: PC = x3456, Mem[x3456] = x6684 Fetch MAR  PC, PC  PC+1 MDR  x6684 IR  MDR Decode Control logic processes the instruction: 0110 011 010 000100 : LDR R3 R2 4 Evaluate Address MAR  R2 + 4

36. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 5 - 36 Instruction Cycle - 2 Operand Fetch MDR  value from memory Execute: none for LDR Store Result R3  MDR