CERN/NA62 GigaTracKer Hybrid Module Manufacturing Fraunhofer Institute for Reliability and Microintegration Gustav-Meyer-Allee 25 13355 Berlin Germany Dipl.-Ing. Thomas Fritzsch Contact: thomas.fritzsch@izm.fraunhofer.de

Fraunhofer IZM – Focus of Activities Substrate Integration Technologies System Integration & Interconnection Technologies PCB Soldering Training/ Qualification and Micro- Mechatronics Materials, Reliability & Sustainable Development Micro Materials Environmental Engineering Wafer Level Integration Technologies Wafer Level Packaging & High Density Interconnects All Silicon System Integration - ASSID System Design System Design & Integration Material characterisation Process evaluation Reliability testing Failure analysis Sample production Training courses

Wafer Level Packaging Technologies Layer Deposition Sputtering, Evaporation Electroplating Photostructuring Resist Polymeric Dielectrics Dry and Wet Etching Chemical Mechanical Polishing Grinding, Saw Dicing Thin Wafer Handling, Wafer Bonding Characterisation, Measurement, Inspection Cleanroom facility 800 sqm

Process Capabilities from 100mm to 200mm (300mm) Sputtering UNAXIS – TiW, Au, Cu, Ti, Cr, CrNi, Al, AlSi Lithography Suess Microtech MA45, MA6, MA200, (MA300) EVG IQ Mask Aligner, EVG spin- and spray coating tools ACS 200 (ACS300) Electroplating SEMITOOL, RENA, Rammgraber Cu, Au, Ni, Sn, SnPb, SnAg, In Waferbonding (oxide, glue, solder, metal) EVG Gemini Dry Etching MATRIX, STS Silicon Etch, STS Oxid Etch Oxide Deposition Thermal Oxide (4“, 6“), PECVD Oxide (6“, 8“) Thinning and Saw Dicing Disco grinding tool, saw dicing for glass and silicon New equipment for several process steps installed until 06/2014

Flip Chip Assembly IZM Competence Flip Chip Sn, SnAg(Cu), CuSn Au/Sn fluxless Gold Indium Thermode Bonding Thermocompression Thermosonic Reflow soldering Flip Chip Assembly Tools Suess FC150 Panasonic FCB3 Datacon Substrates: Chip to Chip Chip To Wafer Wafer to Wafer SnAg CuSn AuSn SnAg AuSn Au ep Nanoporous interconnects Au stud

Hybrid Module Manufacturing Step 1: Sensor wafer processing UBM on silicon sensors Step 2: FE Readout wafer processing Thinning Carrier Wafer Bonding Bumping Laser Release Step 3: Flip Chip Assembly Pick&Place Reflow X-ray Inspection Additional Steps: Module Test Thermal Cycling Metrology In general ROC and sensor has to be connected directly in the shortest way. Therefore flip chip interconnections are the interconnection of choise. Because solder paste printing isn‘t possible in this pitch range below 100µm bumps and pads has to be deposited by electrodeposition.

Wafer Level Packaging for Hybrid Pixel Detectors Deposition of solderable pixel pads on sensor wafer Bump metal Pad metallization SnPb37 Cu-Ni-Au SnAg3.5 Cu, Ni-Cu, Ni-Au Au80Sn20 Au Au Ni Cu FIB cross section of electroplated Cu-Ni-Au pixel pad Formation of Interconnects on Sensor Side: Sputtering of adhesion layer / diffusion barrier (Ti:W) Sputtering of plating base (Cu, Au, Ni, …) Resist patterning by mask lithography UBM deposition (electroplating) Plating base etching Dicing

Equipment for 100/150mm Wafer UBM Plating UNAXIS Sputter Tool: TiW, Cu – Barrier- and Seed Layer (new tool from Oerlikon available) Suess Microtech Mask Aligner MA200/MA6/MA4 Resist Lithography Degussa, RENA, Ramgraber 100 … 200 mm electroplating tool UBM: Cu, Ni (new tools from Ramgraber) Suess Microtech ACS 200 Spin Coater MATRIX Plasma Cleaning Tool (new tool from Oxford) DISCO Dicing Tool

Wafer Level Packaging for Hybrid Pixel Detectors Solder Deposition on Readout Chipwafer SnAg3.5 Indium Cu-Sn Pillar Formation of Interconnect on Readout Chip side: Sputtering of adhesion layer / diffusion barrier (Ti:W, Ti, Cr, …) Sputtering of plating base (Cu, Au, Ni, …) Resist patterning by mask lithography UBM deposition (electroplating, evaporation, …) Solder material deposition (SnPb, SnAg, In, AuSn, CuSn, …) Reflow (optional)

Thin Chip Assembly with Temporary Support Carrier 4. wafer stack dicing 1. Backside grinding 5. Flip chip assembly 2. Support wafer bonding 6. Laser induced debonding 3. Bump deposition 7. Support chip removal

Wafer Thinning Technology Thinning process: Mechanical Si grinding: 2000…4000 grit size, Ra (µm): > 0,014 Stress relief: Dry Polishing Ra (µm): 0,009…0,0003 CMP (Chemical Mechanical Polishing) Wet chemical etching Plasma etching (source DISCO) We also did some experiments with HD3007 regarding this approach. We firstly back ground a IC wafer to the required target thickness of 90µm. After that, we bonded the thin IC wafer with its back ground backside to a non perforated glass wafer. I the next steps, we created solder bumps on the IC wafer by standard wafer bumping technology, to prepare the ICs for flip chip assembly. In the next step, the wafer stack was diced. Dry Polishing CMP Wet Etching Dry Etching (source DISCO)

ECD Waferbumping of Readout Chip Wafer Electroplating Reflow electroplated solder Lithographical patterning of plating resist electroplated UBM sputtered Cu as plating base sputtered Ti/W as adhesion layer and diffusion barrier Al chip pad with overlapped passivation Let me now describe the electrodeposition process more in detail.

Equipment for 200mm Standard Wafer Bumping UNAXIS Sputter Tool: TiW, Cu – Barrier- and Seed Layer Suess Microtech Mask Aligner MA200 Resist Lithography SEMITOOL Equinox 200 mm electroplating tool Cu - SnAg Additional Tools: Suess Microtech ACS 200 Spin Coater MATRIX Plasma Cleaning Tool SSEC Wet Etching Tool AUGUST Optical Wafer Inspection DISCO Thinning and Dicing Tool EVG Gemini Wafer Bonder Tamarack Excimer Laser (new at IZM from 09/2013)

Flip Chip Assembly Flux or tacking medium deposition on sensor (option) Sensor placement in flip chip tool (on carrier) Picking of readout chip (out of waffle pack) ROC placement on sensor Reflow X-ray inspection Panasonic FCB3 Karl Suss FC150

Flip Chip Assembly Karl Suss FC150 Panasonic FCB3 Accuracy: ± 1 µm at 3σ cycle time: ~2 min. per die maximum die size: 2” x 2” maximum substrate size: 6” x 6” heating profiles from top and bottom possible minimum alignment mark size: 20 µm accuracy: 3.5 µm at 3σ full automatic FC bonder with feeder unit cycle time: <2 s maximum substrate size: 300 mm wafer TC and TS bonding head

Flip Chip Assembly Reflow Process Process: Reflow Tools: ATV Solder Reflow Oven 702 (batch oven) Capacity: single carrier process

Laser Debonding of Glass Schott B33 glass wafer Eximer laser:  = 248nm Laser debonding with 248nm UV eximer laser and x-y moving stage (source Tamarack Scientific) Polyimid based glue material Laser light fully absorbed in a 200nm thick glue film – decomposition and opening of the bonding zone (source Schott AG) CTE adapted to Si BF33: 3.25 x 10-6 x 1/K Si: 2.6 x 10-6 x 1/K UV transmittance: 500µm glass wafer ~10%

Flip Chip Assembly X-ray Inspection BILD von der Xray Anlage Process: X-ray scanning of module BILD von der Xray Anlage Tools:Phoenix Nanome|x nanome|x 3D Computed Tomography yes (optional) Maximum Inspection Area 600 mm x 550 mm Real-time Detector Resolution 2 MPixel (optional 4 MPixel) and 24" monitor Detail Detectability <0,3µ (300nm) Maximum Magnification up to 25.000x Automated X-ray Inspection BGA, CSP, QFP, QFN, PTH, Voiding Calulation, Wire Sweep Maximum Tube Voltage 180kV Quelle: http://www.phoenix-xray.com/

Metrology – Planarity Measurement Process: Planarity measurement Tools: DEKTAK Stylus Profiler KLA Tencor P-17 OF+ Surface Profiler Features: Contact Profiling – up to 200mm/ z: 1mm 3D scans – line to line scan (1µm or larger) 3D imaging 2D or 3D stresss analysis Statistics and Analysis (source KLA Tencor)

Daisy Chain Resistance Measurement Manual Probe Station: SUSS-Probe Station with Manipulators 2-point probe needles (4-point possible) AGILENT/Keithley resistance meter

Thermal Cycling Test Programmable temperature test chamber 100 cycles Temperature Range: -20°C/+70°C Temperature gradient: 3-5K/min (source Vötsch-Industrietechnik)

Schedule – Pre-production Task Leadtime 1 Design Dummy Sensor + Readout Chip Wafer 15 2 Dummy Sensor Wafer Processing (5 Wafer) 20 3 Dummy Readout Chip Wafer Processing (5 wafer) 35 4 Dummy Module Flip Chip Assembly 5 Pre-Series Test 40 6 Shipment Total 130 WKs 26 wk 2013 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 1 2 3 4 task 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28   Bonder transfer Chr.Break

Schedule – Production 1, 2 Production 1, 2 (6 full, 15 SC) Leadtime Design Sensor + Readout Chip Wafer 5 Sensor Wafer Processing (8 wafer) Readout Chip Wafer Processing (4 Wafer) 30 Module Flip Chip Assembly (6 full, 15 SC) 15 Production-Series Test 10 Shipment (1 shipments) Total 65 WKs 13 1 2 3 4 5 6 7 8 9 10 11 12 13