STAR Pixel Detector readout prototyping status

LBNL-IPHC-06/ LG22 Talk Outline Quick review of requirements and system design Status at last meeting at IPHC RDO hardware status RDO firmware and software status Future development path

3 RDO Requirements and Design In addition to the detailed requirements imposed by the interface to the sensors, the RDO system shall: Triggered detector system fitting into existing STAR infrastructure (Trigger, DAQ, etc.) Deliver full frame events to STAR DAQ for event building at approximately the same rate as the TPC (1 kHz for DAQ1000). Have live time characteristics such that the Pixel detector is live whenever the TPC is live. Reduce the total data rate of the detector to a manageable level (< TPC rate of ~1MB / event). Reliable, robust, cost effective, etc. Furthermore, this RDO system will be the basis of the future sensor testing including production probe testing so additional functionality will be included to enable this system to have the needed additional capabilities. 3 LBNL-IPHC-06/ LG

4 Pixel Detector Design Ladder with 10 MAPS sensors (~ 2×2 cm each) Mechanical support with kinematic mounts Cabling and cooling infrastructure Detector extraction at one end of the cone New beryllium beam pipe (800 µm thick, r = 2 cm)‏ 2 layers 10 modules 4 ladders/module 4 LBNL-IPHC-06/ LG

5 Functional Data Path – One Ladder buffer JTAG, CLK, CTL, markers buffer This is a highly parallel readout system. 4 ladders per module (RDO motherboard). 10 modules in the PIXEL detector. LU protected power Digital hit data 10 sensors After power-on and configuration, the sensors are run continuously. Triggering is handled in the next stage of the RDO. 1 Ladder 5 LBNL-IPHC-06/ LG

6 Functional Data Path – Phase 1 Each received trigger enables an event buffer for one frame. The system is dead-time free up to the hardware limit of the number of buffers. Highly Parallel FPGA based RDO system 40 sensor outputs/ladder 4 ladders/module 1 RDO board/module 3 RDO boards for Phase-1 prototype test system 6 LBNL-IPHC-06/ LG

7 Functional Data Path – Final (Ultimate) 20 sensor outputs/ladder 4 ladders/module 1 RDO board/module 10 RDO boards for system Each received trigger enables an event buffer for one frame. Triggered event boundaries are determined by data order. Highly Parallel FPGA based RDO system Same hardware with reconfigured firmware 7LBNL-IPHC-06/ LG

8 RDO System Design – Physical Layout 1-2 m Low mass twisted pair 6 m - twisted pair Sensors, Ladders, Modules (interaction point) LU Protected Regulators, Mass cable termination RDO Boards DAQ PCs (Low Rad Area) DAQ Room Power Supplies Platform 30 m 100 m - Fiber optic 30 m Control PCs Platform 30 m 8 LBNL-IPHC-06/ LG

99 RDO Status as of 04/2008 LBNL- IPHC meeting 9 LBNL-IPHC-06/ LG

10 RDO Status - Hardware Hardware – RDO motherboard – Fabricated, tested for individual sensor readout (analog and digital). 3 RDO systems loaded and tested. Mass termination board – Fabricated – under test. Full testing will commence with the readout of a 10 sensor ladder. 1 board loaded. LU protected power boards – Fabricated and tested. 5 boards loaded and tested. Low mass cable – Separate presentation.

LBNL-IPHC-06/ LG11 RDO Status – Firmware and Software Status as shown above.Software is on a parallel path See for full documentationhttp://rnc.lbl.gov/hft/hardware/docs/Phase1/index.html Mimostar-3 Testing Phase-1 ladder Testing Same for all Phase-1 Testing

LBNL-IPHC-06/ LG12 RDO Status – Firmware and Software Phase-1 readout firmware and software are complete and working for analog and digital data for individual sensor testing. DDL optical link and USB based data paths are both functional. Analysis software for Phase-1 data is mostly complete. We are using both Root and Labview based analysis paths. Scripting needed for automated testing of sensors is complete and working. The analysis path for 10 sensor ladders is expected to be a simple extension of the existing framework.

13 Adaptation of the existing individual testing system for use in automated probe testing. Development of the 10 sensor ladder readout firmware and software. Design and implementation of a slow control system for the detector. Extension of the system into multi-ladder / multi- sector readout. RDO Status – Future Development 13 LBNL-IPHC-06/ LG

14 end 14 LBNL-IPHC-06/ LG

15 Parameters and Data Rates ItemNumber Bits/address20 Integration time200 µs Luminosity8 × Hits / frame on Inner sensors (r=2.5 cm) 246 Hits / frame on Outer sensors (r=8.0 cm) 24 Final sensors (Inner ladders)100 Final sensors (Outer ladders)300 Event format overheadTBD Average Pixels / Cluster2.5 Average Trigger rate1 kHz ItemNumber Bits/address20 Integration time640 µs Luminosity3 × Hits / frame on Inner sensors (r=2.5 cm) 295 Hits / frame on Outer sensors (r=8.0 cm) 29 Phase-1 sensors (Inner ladders)100 Phase-1 sensors (Outer ladders)300 Event format overheadTBD Average Pixels / Cluster2.5 Average Trigger rate1 kHz Phase-1Final (Ultimate) Raw data rate from sensors = 32 GB/sec Data rate to storage = 237 MB/sec (Scaled to full size detector) Data rate to storage = 199 MB/sec Note: Data rates for hit data only for Au-Au central collisions including peripheral collision electrons. Sensor noise is not included. ItemNumber Bits/address20* Integration time640 µs Luminosity3 × Hits / frame on Inner sensors (r=2.5 cm)295 Hits / frame on Outer sensors (r=8.0 cm)29 Phase-1 sensors (Inner ladders)100 Phase-1 sensors (Outer ladders)300 Event format overheadTBD Average Pixels / Cluster2.5 Average Trigger rate1 kHz ItemNumber Bits/address20* Integration time200 µs Luminosity8 × Hits / frame on Inner sensors (r=2.5 cm)246 Hits / frame on Outer sensors (r=8.0 cm)24 Final sensors (Inner ladders)100 Final sensors (Outer ladders)300 Event format overheadTBD Average Pixels / Cluster2.5 Average Trigger rate1 kHz 15 LBNL-IPHC-06/ LG

16 DDL Controller USB Controller Command decoder Event builder Frame FIFO ADCLVDSSPARE IO SRAM controller Global control register(access every module) Temperature ADC Internal processor(conta ct outside by SPARE IO) TCD This is the block diagram of firmware structure of pixel readout board Thick arrow means connection to outside of FPGA Block which connects to outside of FPGA includes IO pins and controller. Cross lines denotes NO connection. 16 LBNL-IPHC-06/ LG