A Design Flow for Optimal Circuit Design Using Resource and Timing Estimation Farnaz Gharibian and Kenneth B. Kent {f.gharibian, unb.ca Faculty of Computer Science, University of New Brunswick Introduction There are two important constraints that should be considered by hardware designers using Field Programmable Gate Arrays (FPGAs): Fitting the design inside the specified FPGAs Meeting the frequency constraints The hardware designers need to be aware of the number of resources consumed by the design because the number of logic elements and routing resources may vary across different FPGA devices. Global Estimation module gets a CDFG that is created from the Handel-C language and calculates the area and delay for the desired design. Update module updates the working model of hardware definition for further iterations of the estimation process. Local Estimation module is used during the optimization process and gives the area and delay for the optimized part of the program to the designer. Optimization module finds parallelism that exists in a given high level hardware definition. Apply module applies changes to hardware definition once estimation determines that there are enough resources. Handel-C Parse Tree Global Estimation Apply? Synthesis Tool Yes Optimization Update? Place & Route Local Estimation No Yes No Estimation Tools Information about design time and area consumption is not available for the designer until after the synthesis, place and route stages have been completed. This process takes time. The increase in FPGA density allows larger and more complex circuits to be implemented, therefore the process time is expected to increase. Estimation Tools are needed to help the designer during the hardware design process. They provide a Fast evaluation about the area and time consumption of the design. Proposed Framework Estimation tools are used in different areas such as hardware/software partitioning, generating IP cores and high level languages. A programmer who uses high level languages to define the design in hardware should consider potential parallelism in the code and optimize the code to get higher performance. There is a trade-off between optimization and circuit space. The programmer continues to apply optimization as long as the design still fits in the FPGA. The resource estimation tools at design time help the programmer with this process. Our proposed framework, shown in the Figure below, helps programmers to improve their design performances and to decrease their design development time. Two major goals are considered: 1) dynamically identifying parallelism; 2) considering the available resources. Conclusions We have designed a hybrid model for our proposed estimation tool. The estimation tool consists of two models: Global Estimation and Local Estimation. Different estimation methods are used for each estimation module in our proposed tool. Global Estimation should be very accurate to give the resource estimation for the whole design. Local estimation should be very fast to facilitate the optimization process. High Level View of the Proposed Framework