1. Introducing the Nexys 2 Board CS 332 – Operating Systems 12/04/2011 by Otto Castell-R

2. FPGA FPGA – Field Programmable Gate Array Integrated Circuit which can be configured by the user Integrated Circuit which can be configured by the user Configuration is done using HDL (Hardware Description Language) Configuration is done using HDL (Hardware Description Language) FPGA's can be programmed to implement any logic function FPGA's can be programmed to implement any logic function User designs the logic circuits using AND, OR and NOT Logic Gates, which the circuit board translates into universal gates (NAND, NOR) User designs the logic circuits using AND, OR and NOT Logic Gates, which the circuit board translates into universal gates (NAND, NOR)

3. FPGA > Nexys 2

4. Logic Gates A logic gate is a physical model of a Boolean function and exists as: Elementary Gate Elementary Gate Universal Gate Universal Gate

5. Logic Gates – Half Adder

6. Logic Gates – Half Adder > SHDL module half_adder (a, b : s, r) s = /a*b+a*/b ; r = a*b ; end module

7. Logic Gates – Half Adder > SHDL library IEEE; library UNISIM; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity half_adder is port ( a : in std_logic ; b : in std_logic ; s : out std_logic ; r : out std_logic ); end half_adder; architecture synthesis of half_adder is begin -- concurrent statements s <= ((not a) and b) or (a and (not b)) ; r <= a and b ; end synthesis;

8. Logic Gates – Full Adder