Caltech CS184 Winter DeHon 1 CS184a: Computer Architecture (Structure and Organization) Day 6: January 22, 2003 VLSI Scaling

Caltech CS184 Winter DeHon 2 Today VLSI Scaling Rules Effects Historical/predicted scaling Variations (cheating) Limits

Caltech CS184 Winter DeHon 3 Why Care? In this game, we must be able to predict the future Rapid technology advance Reason about changes and trends re-evaluate prior solutions given technology at time X.

Caltech CS184 Winter DeHon 4 Why Care Cannot compare against what competitor does today –but what they can do at time you can ship Careful not to fall off curve –lose out to someone who can stay on curve

Caltech CS184 Winter DeHon 5 Scaling Premise: features scale “uniformly” –everything gets better in a predictable manner Parameters:   (lambda) -- Mead and Conway (class)  S -- Bohr  1/  -- Dennard

Caltech CS184 Winter DeHon 6 Feature Size is half the minimum feature size in a VLSI process [minimum feature usually channel width]

Caltech CS184 Winter DeHon 7 Scaling Channel Length (L) Channel Width (W) Oxide Thickness (T ox ) Doping (N a ) Voltage (V)

Caltech CS184 Winter DeHon 8 Scaling Channel Length (L) Channel Width (W) Oxide Thickness (T ox ) Doping (N a ) 1/ Voltage (V)

Caltech CS184 Winter DeHon 9 Effects? Area Capacitance Resistance Threshold (V th ) Current (I d ) Gate Delay (  gd ) Wire Delay (  wire ) Power

Caltech CS184 Winter DeHon 10 Area       L * W        m   m  50% area  2x capacity same area

Caltech CS184 Winter DeHon 11 Area Perspective [2000 tech.] 18mm  18mm 0.18  m 60G 

Caltech CS184 Winter DeHon 12 Capacity Scaling from Intel

Caltech CS184 Winter DeHon 13 Capacitance Capacitance per unit area –C ox =  SiO 2 /T ox –T ox   T ox /  –C ox   C ox

Caltech CS184 Winter DeHon 14 Capacitance Gate Capacitance  C gate = A*C ox       C ox   C ox  C gate   C gate / 

Caltech CS184 Winter DeHon 15 Threshold Voltage

Caltech CS184 Winter DeHon 16 Threshold Voltage V TH   V TH 

Caltech CS184 Winter DeHon 17 Current Saturation Current –I d =(  C OX /2)(W/L)(V gs -V TH ) 2 –V gs= V   V  –V TH   V TH  –W   W  –C ox   C ox –I d   I d 

Caltech CS184 Winter DeHon 18 Gate Delay   gd =Q/I=(CV)/I  V   V   I d   I d  C C /C C /   gd   gd / 

Caltech CS184 Winter DeHon 19 Resistance R=  L/(W*t) W   W  L, t similar R   R

Caltech CS184 Winter DeHon 20 Wire Delay   wire =R  C  R  R  C  C /    wire  wire …assuming (logical) wire lengths remain constant... Assume short wire or buffered wire (unbuffered wire ultimately scales as length squared)

Caltech CS184 Winter DeHon 21 Power Dissipation (Static) Resistive Power –P=V*I –V   V  –I d   I d  –P   P  

Caltech CS184 Winter DeHon 22 Power Dissipation (Dynamic) Capacitive (Dis)charging  P=(1/2)CV 2 f  V   V   C   C /   P   P   Increase Frequency?  f   f ?  P   P  

Caltech CS184 Winter DeHon 23 Effects? Area 1/   Capacitance 1/  Resistance  Threshold (V th ) 1/  Current (I d ) 1/  Gate Delay (  gd ) 1/  Wire Delay (  wire ) 1 Power 1/     1/  

Caltech CS184 Winter DeHon 24 ITRS Roadmap Semiconductor Industry rides this scaling curve Try to predict where industry going –(requirements…self fulfilling prophecy)

Caltech CS184 Winter DeHon 25 MOS Transistor Scaling (1974 to present) S=0.7 [0.5x per 2 nodes] Pitch Gate Source: 2001 ITRS - Exec. Summary, ORTC Figure [from Andrew Kahng]

Caltech CS184 Winter DeHon 26 Half Pitch (= Pitch/2) Definition (Typical MPU/ASIC) (Typical DRAM) Poly Pitch Metal Pitch Source: 2001 ITRS - Exec. Summary, ORTC Figure [from Andrew Kahng]

Caltech CS184 Winter DeHon > 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> x 0.7x NN+1N+2 Node Cycle Time (T yrs): *CARR(T) = [(0.5)^(1/2T yrs)] - 1 CARR(3 yrs) = -10.9% CARR(2 yrs) = -15.9% * CARR(T) = Compound Annual Reduction Rate cycle time period, T) Log Half-Pitch Linear Time 1994 NTRS -.7x/3yrs Actual -.7x/2yrs Scaling Calculator + Node Cycle Time: Source: 2001 ITRS - Exec. Summary, ORTC Figure [from Andrew Kahng]

Caltech CS184 Winter DeHon 28 Source: 2001 ITRS - Exec. Summary, ORTC Figure [from Andrew Kahng]

Caltech CS184 Winter DeHon 29 Delays? If delays in gates/switching? If delays in interconnect? Logical interconnect lengths?

Caltech CS184 Winter DeHon 30 Delays? If delays in gates/switching? –Delay reduce with 1/ 

Caltech CS184 Winter DeHon 31 Delays Logical capacities growing Wirelengths? –No locallity   (slower!) –Rent’s Rule L   n (p-0.5) [p>0.5]

Caltech CS184 Winter DeHon 32 Compute Density Density = compute / (Area * Time)   >compute density scaling>     gates dominate, p<0.5    moderate p, good fraction of gate delay –[p from Rent’s Rule again – more on Day12]    large p (wires dominate area and delay)

Caltech CS184 Winter DeHon 33 Power Density P  P   (static, or increase frequency) P  P   (dynamic, same freq.)   P/A   P/A … or … P/  A

Caltech CS184 Winter DeHon 34 Cheating… Don’t like some of the implications –High resistance wires –Higher capacitance –Need for more wiring –Not scale speed fast enough

Caltech CS184 Winter DeHon 35 Improving Resistance R=  L/(W*t) W   W  L, t similar R   R  Don’t scale t quite as fast.  Decrease  (copper)

Caltech CS184 Winter DeHon 36 Improving Capacitance Capacitance per unit area –C ox =  SiO 2 /T ox –T ox   T ox /  –C ox   C ox Reduce Dielectric Constant 

Caltech CS184 Winter DeHon 37 Wire Layers = More Wiring

Caltech CS184 Winter DeHon 38 Wire Via Global (up to 5) Intermediate (up to 4) Local (2) Passivation Dielectric Etch Stop Layer Dielectric Capping Layer Copper Conductor with Barrier/Nucleation Layer Pre Metal Dielectric Tungsten Contact Plug Typical chip cross-section illustrating hierarchical scaling methodology [from Andrew Kahng]

Caltech CS184 Winter DeHon 39 Improving Gate Delay   gd =Q/I=(CV)/I  V   V   I d =(  C OX /2)(W/L)(V gs -V TH ) 2  I d   I d  C C /C C /   gd   gd /   Lower C.  Don’t scale V. Don’t scale V: V  V I   I  gd   gd /  2

Caltech CS184 Winter DeHon 40 …But Power Dissipation (Dynamic) Capacitive (Dis)charging  P=(1/2)CV 2 f  V   V   C   C /   P   P   Increase Frequency?  f   f ?  P   P   If not scale V, power dissipation not scale.

Caltech CS184 Winter DeHon 41 …And Power Density P   P (increase frequency) P   P   (dynamic, same freq.)     P/A   P/A … or …   P/A Power Density Increases

Caltech CS184 Winter DeHon 42 Physical Limits Doping? Features?

Caltech CS184 Winter DeHon 43 Physical Limits Depended on –bulk effects doping current (many electrons) mean free path in conductor –localized to conductors Eventually –single electrons, atoms –distances close enough to allow tunneling

Caltech CS184 Winter DeHon 44 What Is A “Red Brick” ? Red Brick = ITRS Technology Requirement with no known solution Alternate definition: Red Brick = something that REQUIRES billions of dollars in R&D investment [from Andrew Kahng]

Caltech CS184 Winter DeHon 45 The “ Red Brick Wall ” ITRS vs 1999 Source: Semiconductor International - [from Andrew Kahng]

Caltech CS184 Winter DeHon 46 Finishing Up...

Caltech CS184 Winter DeHon 47 Big Ideas [MSB Ideas] Moderately predictable VLSI Scaling –unprecedented capacities/capability growth for engineered systems –change –be prepared to exploit –account for in comparing across time

Caltech CS184 Winter DeHon 48 Big Ideas [MSB-1 Ideas] Uniform scaling reasonably accurate for past couple of decades Area increase   –Real capacity maybe a little less? Gate delay decreases (1/  ) Wire delay not decrease, maybe increase Overall delay decrease less than (1/  )