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Penn ESE534 Spring2014 -- Mehta & DeHon 1 ESE534 Computer Organization Day 6: February 12, 2014 Energy, Power, Reliability.

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Presentation on theme: "Penn ESE534 Spring2014 -- Mehta & DeHon 1 ESE534 Computer Organization Day 6: February 12, 2014 Energy, Power, Reliability."— Presentation transcript:

1 Penn ESE534 Spring2014 -- Mehta & DeHon 1 ESE534 Computer Organization Day 6: February 12, 2014 Energy, Power, Reliability

2 Penn ESE534 Spring2014 -- Mehta & DeHon 2 Today Energy tradeoffs Voltage limits and leakage Variations [more of the gory transistor equations…]

3 Penn ESE534 Spring2014 -- Mehta & DeHon 3 At Issue Many now argue energy will be the ultimate scaling limit –(not lithography, costs, …) Proliferation of portable and handheld devices –…battery size and life biggest issues Cooling, energy costs may dominate cost of electronics –Even server room applications

4 Preclass 1 1GHz case –Voltage? –Energy per Operation? –Power required for 2 processors? 2GHz case –Voltage? –Energy per Operation? –Power required for 1 processor? Penn ESE534 Spring2014 -- Mehta & DeHon 4

5 Preclass 1 Lesson What does Preclass 1 result tell us? Penn ESE534 Spring2014 -- Mehta & DeHon 5

6 6 Energy and Delay  gd =Q/I=(CV)/I I d,sat =(  C OX /2)(W/L)(V gs -V TH ) 2

7 Penn ESE534 Spring2014 -- Mehta & DeHon 7 Energy/Delay Tradeoff E  V 2  gd  1/V We can trade speed for energy E×(  gd ) 2  constant Martin et al. Power-Aware Computing, Kluwer 2001 http://caltechcstr.library.caltech.edu/308/  gd =(CV)/I I d,sat  (V gs -V TH ) 2

8 Penn ESE534 Spring2014 -- Mehta & DeHon 8 Area/Time Tradeoff Also have Area-Time tradeoffs –HW2 spatial vs temporal multipliers –See more next week Compensate slowdown with additional parallelism …trade Area for Energy  Architectural Option

9 Penn ESE534 Spring2014 -- Mehta & DeHon 9 Question By how much can we reduce energy? What limits us?

10 Penn ESE534 Spring2014 -- Mehta & DeHon 10 Challenge: Power

11 Penn ESE534 Spring2014 -- Mehta & DeHon 11 Origin of Power Challenge Limited capacity to remove heat –~100W/cm 2 force air –1-10W/cm 2 ambient Transistors per chip grow at Moore’s Law rate = (1/F) 2 Energy/transistor must decrease at this rate to keep constant power density P/tr  CV 2 f E/tr  CV 2 –…but V scaling more slowly than F

12 Penn ESE534 Spring2014 -- Mehta & DeHon 12 ITRS V dd Scaling: More slowly than F

13 Penn ESE534 Spring2014 -- Mehta & DeHon 13 ITRS CV 2 Scaling: More slowly than (1/F) 2

14 Penn ESE534 Spring2014 -- Mehta & DeHon 14 Origin of Power Challenge Transistors per chip grow at Moore’s Law rate = (1/F) 2 Energy/transistor must decrease at this rate to keep constant E/tr  CV 2

15 Penn ESE534 Spring2014 -- Mehta & DeHon 15 Historical Power Scaling [Horowitz et al. / IEDM 2005]

16 Microprocessor Power Density Penn ESE534 Spring2014 -- Mehta & DeHon 16 The Future of Computing Performance: Game Over or Next Level? National Academy Press, 2011 http://www.nap.edu/catalog.php?record_id=12980 Watts

17 Intel Power Density Penn ESE534 Spring2014 -- Mehta & DeHon 17

18 Penn ESE534 Spring2014 -- Mehta & DeHon 18 Source: Carter/Intel 18 Power Limits Integration Impact

19 Power density is limiting scaling –Can already place more transistors on a chip than we can afford to turn on! Power is potential challenge/limiter for all future chips. –Only turn on small percentage of transistors? –Operate those transistors as much slower frequency? –Find a way to drop V dd ? Penn ESE534 Spring2014 -- Mehta & DeHon 19

20 Penn ESE534 Spring2014 -- Mehta & DeHon 20 How far can we reduce V dd ?

21 Penn ESE534 Spring2014 -- Mehta & DeHon 21 Limits Ability to turn off the transistor Parameter Variations Noise (not covered today)

22 MOSFET Conduction Penn ESE534 Spring2014 -- Mehta & DeHon 22 From: http://en.wikipedia.org/wiki/File:IvsV_mosfet.png

23 Transistor Conduction Penn ESE534 Spring2014 -- Mehta & DeHon 23 Three regions –Subthreshold (V gs <V TH ) –Linear (V gs >V TH ) and (V ds < (V gs -V TH )) –Saturation (V gs >V TH ) and (V ds > (V gs -V TH ))

24 Saturation Region Penn ESE534 Spring2014 -- Mehta & DeHon 24 I ds,sat =(  C OX /2)(W/L)(V gs -V TH ) 2 (V gs >V TH ) (V ds > (V gs -V TH ))

25 Linear Region Penn ESE534 Spring2014 -- Mehta & DeHon 25 I ds,lin =(  C OX )(W/L)((V gs -V TH )V ds -(V ds ) 2 /2) (V gs >V TH ) (V ds < (V gs -V TH ))

26 Penn ESE534 Spring2014 -- Mehta & DeHon 26 Subthreshold Region (V gs <V TH ) [Frank, IBM J. R&D v46n2/3p235]

27 Operating a Transistor Concerned about I on and I off I on drive (saturation) current for charging –Determines speed: T gd = CV/I I off leakage current –Determines leakage power/energy: P leak = V×I leak E leak = V×I leak ×T cycle Penn ESE534 Spring2014 -- Mehta & DeHon 27

28 Penn ESE534 Spring2014 -- Mehta & DeHon 28 Leakage To avoid leakage want I off very small Switch V from V dd to 0 V gs in off state is 0 (V gs <V TH )

29 Penn ESE534 Spring2014 -- Mehta & DeHon 29 Leakage S  90mV for single gate S  70mV for double gate For lowest leakage, want S small, V TH large 4 orders of magnitude I VT /I off  V TH >280mV Leakage limits V TH in turn limits V dd

30 How maximize I on /I off ? Maximize I on /I off – for given V dd ? E sw  CV 2 Get to pick V TH, V dd Penn ESE534 Spring2014 -- Mehta & DeHon 30 I d,lin =(  C OX )(W/L)(V gs -V TH )V ds -(V ds ) 2 /2 I d,sat =(  C OX /2)(W/L)(V gs -V TH ) 2

31 Preclass 2 E = E sw + E leak E leak = V×I leak ×T cycle E sw  CV 2 I chip-leak = N devices ×I tr-leak Penn ESE534 Spring2014 -- Mehta & DeHon 31

32 Preclass 2 E leak (V) ? T cycle (V)? Penn ESE534 Spring2014 -- Mehta & DeHon 32

33 In Class Assign calculations –SIMD – each student computes for a different Voltage Collect results on board Group: Identify minimum energy point and discuss Penn ESE534 Spring2014 -- Mehta & DeHon 33

34 Values VT(v)Esw(V)Eleak(V)E(V) 0.363.6E-091.296E-091.296E-111.30896E-09 0.270.0000000277.29E-107.29E-118.019E-10 0.245.17064E-085.76E-101.24095E-107.00095E-10 0.219.74734E-084.41E-102.04694E-106.45694E-10 0.2051.08137E-074.2025E-102.21682E-106.41932E-10 0.21.19897E-074E-102.39794E-106.39794E-10 0.191.4711E-073.61E-102.79509E-106.40509E-10 0.180.000000183.24E-10 6.48E-10 0.153.23165E-072.25E-104.84748E-107.09748E-10 0.125.56991E-071.44E-106.68389E-108.12389E-10 0.090.00000098.1E-118.1E-108.91E-10 Penn ESE534 Spring2014 -- Mehta & DeHon 34

35 Graph for In Class Penn ESE534 Spring2014 -- Mehta & DeHon 35

36 Impact Subthreshold slope prevents us from scaling voltage down arbitrarily. Induces a minimum operating energy. Penn ESE534 Spring2014 -- Mehta & DeHon 36

37 Penn ESE534 Spring2014 -- Mehta & DeHon 37 Challenge: Variation

38 Penn ESE534 Spring2014 -- Mehta & DeHon 38 Statistical Dopant Count and Placement [Bernstein et al, IBM JRD 2006]

39 Penn ESE534 Spring2014 -- Mehta & DeHon 39 V th Variability @ 65nm [Bernstein et al, IBM JRD 2006]

40 Penn ESE534 Spring2014 -- Mehta & DeHon 40 Variation Fewer dopants, atoms  increasing Variation How do we deal with variation? 40 % variation in V TH (From ITRS prediction)

41 Penn ESE534 Spring2014 -- Mehta & DeHon 41 Impact of Variation? Higher V TH ? –Not drive as strongly  slower –I d,sat  (V gs -V TH ) 2 Lower V TH ? –Not turn off as well  leaks more

42 Penn ESE534 Spring2014 -- Mehta & DeHon 42 Variation Margin for expected variation Must assume V TH can be any value in range Probability Distribution V TH I on,min =I on ( Vth,max ) I d,sat  (V gs -V TH ) 2 V gs = V dd

43 Penn ESE534 Spring2014 -- Mehta & DeHon 43 Margining Must raise V dd to increase drive strength Increase energy Probability Distribution V TH I on,min =I on ( Vth,max ) I d,sat  (V gs -V TH ) 2 V gs = V dd

44 Penn ESE534 Spring2014 -- Mehta & DeHon 44 Variation Increasing variation forces higher voltages –On top of our leakage limits 44

45 Penn ESE534 Spring2014 -- Mehta & DeHon 45 Margins growing due to increasing variation Margined value may be worse than older technology? Variations Probability Distribution Delay New Old

46 Penn ESE534 Spring2014 -- Mehta & DeHon 46 End of Energy Scaling? [Bol et al., IEEE TR VLSI Sys 17(10):1508—1519] Black nominal Grey with variation

47 Chips Growing Larger chips (billions of transistors)  sample further out on distribution curve Penn ESE534 Spring2014 -- Mehta & DeHon 47 From: http://en.wikipedia.org/wiki/File:Standard_deviation_diagram.svg

48 Penn ESE534 Spring2014 -- Mehta & DeHon 48 Big Ideas Can trade time for energy –… area for energy Variation and leakage limit voltage scaling Power major limiter going forward –Can put more transistors on a chip than can switch Continued scaling demands –Deal with noisier components High variation … other noise sources

49 Admin Homework 2 due Tonight Reading for Monday on web Homework 3 due next Wednesday Penn ESE534 Spring2014 -- Mehta & DeHon 49

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