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CS184a: Computer Architecture (Structure and Organization)

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1 CS184a: Computer Architecture (Structure and Organization)
Day 17: February 15, 2005 Interconnect 5: Meshes Caltech CS184 Winter DeHon

2 Previous Saw we needed to exploit locality/structure in interconnect
Saw a mesh might be useful Question: how does w grow? Saw Rent’s Rule as a way to characterize structure Caltech CS184 Winter DeHon

3 Today Mesh: Channel width bounds Linear population Switch requirements
Routability Segmentation Clusters Commercial Caltech CS184 Winter DeHon

4 Mesh Caltech CS184 Winter DeHon

5 Mesh Channels Lower Bound on w? Bisection Bandwidth BW  Np
N0.5 channels in bisection Caltech CS184 Winter DeHon

6 Straight-forward Switching Requirements
Switching Delay? Total Switches? Caltech CS184 Winter DeHon

7 Switch Delay Switching Delay: 2 (Nsubarray) worst case: Nsubarray = N
Caltech CS184 Winter DeHon

8 Total Switches Switches per switchbox: 4 3ww / 2 = 6w2
Bidirectional switches (NW same as WN) double count Caltech CS184 Winter DeHon

9 Total Switches Switches per switchbox: Switches into network:
4 3ww / 2 = 6w2 Switches into network: (K+1) w Switches per PE: 6w2 +(K+1) w w = cNp-0.5 Total  N2p-1 Total Switches: N*(Sw/PE)  N2p Caltech CS184 Winter DeHon

10 Routability? Asking if you can route in a given channel width is:
NP-complete Caltech CS184 Winter DeHon

11 Traditional Mesh Population
Switchbox contains only a linear number of switches in channel width Caltech CS184 Winter DeHon

12 Linear Mesh Switchbox Each entering channel connect to:
One channel on each remaining side (3) 4 sides W wires Bidirectional switches (NW same as WN) double count 34W/2=6W switches vs. 6w2 for full population Caltech CS184 Winter DeHon

13 Total Switches Switches per switchbox: Switches into network:
(K+1) w Switches per PE: 6w +(K+1) w w = cNp-0.5 Total  Np-0.5 Total Switches: N*(Sw/PE)  Np+0.5 > N Caltech CS184 Winter DeHon

14 Total Switches  Np+0.5 N < Np+0.5 < N2p Total Switches
Switches grow faster than nodes Wires grow faster than switches Caltech CS184 Winter DeHon

15 Checking Constants Wire pitch = 8l switch area = 2500 l2
wire area: (8w)2 switch area: 62500 w crossover w=234 ? (practice smaller) Caltech CS184 Winter DeHon

16 Checking Constants: Full Population
Wire pitch = 8l switch area = 2500 l2 wire area: (8w)2 switch area: 62500 w2 effective wire pitch: 120 l ~15 times pitch Caltech CS184 Winter DeHon

17 Practical Just showed: Can afford to not use some wires perfectly
would take 15 Mapping Ratio for linear population to take same area as full population (once crossover to wire dominated) Can afford to not use some wires perfectly to reduce switches Caltech CS184 Winter DeHon

18 Diamond Switch Typical switchbox pattern:
Used by Xilinx Many less switches, but cannot guarantee will be able to use all the wires may need more wires than implied by Rent, since cannot use all wires this was already true…now more so Caltech CS184 Winter DeHon

19 Universal SwitchBox Same number of switches as diamond
Locally: can guarantee to satisfy any set of requests request = direction through swbox as long as meet channel capacities and order on all channels irrelevant can satisfy Not a global property no guarantees between swboxes Caltech CS184 Winter DeHon

20 Diamond vs. Universal? Universal routes strictly more configurations
Caltech CS184 Winter DeHon

21 Inter-Switchbox Constraints
Channels connect switchboxes For valid route, must satisfy all adjacent switchboxes Caltech CS184 Winter DeHon

22 Mapping Ratio? How bad is it? How much wider do channels have to be?
detail channel width required / global ch width Caltech CS184 Winter DeHon

23 Mapping Ratio Empirical: Theory/provable:
Seems plausible, constant in practice Theory/provable: There is no Constant Mapping Ratio At least detail/global can be arbitrarily large! Caltech CS184 Winter DeHon

24 Domain Structure Once enter network (choose color) can only switch within domain Caltech CS184 Winter DeHon

25 Detail Routing as Coloring
Caltech CS184 Winter DeHon

26 Detail Routing as Coloring
Global Route channel width = 2 Detail Route channel width = N Can make arbitrarily large difference Caltech CS184 Winter DeHon

27 Detail Routing as Coloring
Caltech CS184 Winter DeHon

28 Routability Domain Routing is NP-Complete
can reduce coloring problem to domain selection i.e. map adjacent nodes to same channel Previous example shows basic shape (another reason routers are slow) Caltech CS184 Winter DeHon

29 Routing Lack of detail/global mapping ratio
Says detail can be arbitrarily worse than global Say global not necessarily predict detail Argument against decomposing mesh routing into global phase and detail phase Modern FPGA routers do not Caltech CS184 Winter DeHon

30 Segmentation To improve speed (decrease delay)
Allow wires to bypass switchboxes Maybe save switches? Certainly cost more wire tracks Caltech CS184 Winter DeHon

31 Buffered Delay Lseg  104 sq. 10 segments:
Day 13 Buffered Delay Chip: 7mm side, 70nm sq. (45nm process) 105 squares across chip Lseg  104 sq. 10 segments: Each of delay 2 Tgate Tcross = 2030ps = 600ps Compare: 4ns Caltech CS184 Winter DeHon

32 Delay through Switching
Day 13 Delay through Switching 0.6 mm CMOS How far in GHz clock cycle? Caltech CS184 Winter DeHon

33 Segmentation Segment of Length Lseg 6 switches per switchbox visited
Only enters a switchbox every Lseg SW/sbox/track of length Lseg = 6/Lseg Caltech CS184 Winter DeHon

34 Segmentation Reduces switches on path N/Lseg May get fragmentation
Another cause of unusable wires Caltech CS184 Winter DeHon

35 Segmentation: Corner Turn Option
Can you corner turn in the middle of a segment? If can, need one more switch SW/sbox/track = 5/Lseg + 1 Caltech CS184 Winter DeHon

36 VPR Segment 4 Pix Caltech CS184 Winter DeHon

37 VPR Segment 4 Route Caltech CS184 Winter DeHon

38 C-Box Depopulation Not necessary for every input to connect to every channel Saw last time: K(N-K+1) switches Maybe use less? Caltech CS184 Winter DeHon

39 IO Population Toronto Model IOs spread over 4 sides
Fc fraction of tracks which an input connects to IOs spread over 4 sides Maybe show up on multiple Shown here: 2 Caltech CS184 Winter DeHon

40 IO Population Caltech CS184 Winter DeHon

41 Leaves Not LUTs Recall cascaded LUTs
Often group collection of LUTs into a Logic Block Caltech CS184 Winter DeHon

42 Logic Block [Betz+Rose/IEEE D&T 1998]
Caltech CS184 Winter DeHon

43 Cluster Size [Betz+Rose/IEEE D&T 1998]
Caltech CS184 Winter DeHon

44 Inputs Required per Cluster
Should it be linear? [Betz+Rose/IEEE D&T 1998] Caltech CS184 Winter DeHon

45 Review: Mesh Design Parameters
Cluster Size Internal organization LB IO (Fc, sides) Switchbox Population and Topology Segment length distribution Switch rebuffering Caltech CS184 Winter DeHon

46 Commercial Parts Caltech CS184 Winter DeHon

47 XC4K Interconnect Caltech CS184 Winter DeHon

48 XC4K Interconnect Details
Caltech CS184 Winter DeHon

49 Virtex II Caltech CS184 Winter DeHon

50 Virtex II Interconnect Resources
Caltech CS184 Winter DeHon

51 Big Ideas [MSB Ideas] Mesh natural 2D topology
Channels grow as W(Np-0.5) Wiring grows as W(N2p ) Linear Population: Switches grow as W(Np+0.5) Worse than shown for hierarchical Unbounded globaldetail mapping ratio Detail routing NP-complete Caltech CS184 Winter DeHon

52 Big Ideas [MSB-1 Ideas] Segmented/bypass routes
can reduce switching delay costs more wires (fragmentation of wires) Caltech CS184 Winter DeHon

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