By: C. Eldracher, T. McKee, A Morrill, R. Robson. Supervised by: Professor Shams

 Microprocessor, are the most used device  Power consumption has been an increasing desire in the modern age  As our technology becomes smaller, we want the ability for it to become mobile as well  This opens up the possibility to run complex devices on low power supplies, such as phones

 16 microprocessor, so we have 16 bit register and 16 bit data bus.  Running the circuit at minimal V DD  Optimize power

Memory: Adam Control Unit: Tom ALU: Chris Register File: Reece Break down of Microprocessor

 To familiarize oneself with the various methodologies of design  We decided upon comparing different methodologies of designs and weighing their benefits and detriments  Specifically: Programmable logic, Semi- Custom, Fully Custom

Programmable LogicSemi-CustomCustom Low Market timeMedian market timeHigh Market time Low CostMedian CostHigh cost High static power consumption (78.9 mW) Median power consumption Optimized for power consumption Low clock optimization (127 MHz) Median clock speedOptimized Clock speed Low costMedian costCostly to manufacture

 Transistor count per One Memory Cell (holds one bit) can be designed with 4,6 or12 transistor  Transistor width and length sizing was increased to reduce power consumption and increase speed  Total memory bits 32Kbits

 To reduce power consumptions  Reduce the lengths of interconnected and  This reduce the internal capacitance and resistance which are power hungry  Using Tri-state buffer and 2 input decoder to reduce wire length and power consumption

 Dividing op code into 3 parts to remove redundant logic.  Various design attempts original taken from a simple DEMUX.  Minimizing wiring capacitance.

 Minimizing the total amount of gate and inverters to minimize power consumption.  Testing to make sure enables would work on low voltage  Replacing transmission gates with tri-state buffers.

 Generation of Logic process used for the processor ◦ ALU design is working on less logical operational blocks, but is still able to perform proper basic functionalities ◦ ALU is divided into two major block sets, shifting and Adder/subtractor ◦ Logical testing on the schematics was successful in all blocks of the ALU system.

 Difficult to maintain logic while trying to decrease number of transistors.  Trying to divide blocks to reduce the number of transistors and the power  Currently working to optimize each block to decrease power requirements.

 Holds data currently in use by the ALU  Very fast  Made of many D flip-flops  Each D flip-flop holds one bit  Need 16 flip-flops in each register  Register must be parallel-in, parallel-out

 Interfacing of components, account for delay.  Optimization  Poster  Final report  Comparison of code  Changing V DD and speed.  Custom design of a microprocessor in order to reduce power comparative study.

 Familiarization with cadence  Research into low power transistor design\how a microprocessor works  Programmable logic, synopsis generated circuit, Custom schematic, custom layout.  Comparison between the different implementation techniques.

Questions?