Copyright Agrawal, 2007ELEC6270 Spring 09, Lecture 71 ELEC 5270/6270 Spring 2009 Low-Power Design of Electronic Circuits Power Analysis: High-Level Vishwani.

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Copyright Agrawal, 2007ELEC6270 Spring 09, Lecture 71 ELEC 5270/6270 Spring 2009 Low-Power Design of Electronic Circuits Power Analysis: High-Level Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL

Copyright Agrawal, 2007ELEC6270 Spring 09, Lecture 72 Key Parameters Capacitance Capacitance Area Area Complexity Complexity Activity Activity Dynamic behavior Dynamic behavior Operational characteristics Operational characteristics Power α Capacitance × Activity

Copyright Agrawal, 2007ELEC6270 Spring 09, Lecture 73 Architecture-Level Power Estimation Analytical methods Analytical methods Complexity-based models Complexity-based models Activity-based models Activity-based models Empirical methods Empirical methods Fixed-activity models Fixed-activity models Activity-sensitive models Activity-sensitive models

Copyright Agrawal, 2007ELEC6270 Spring 09, Lecture 74 A Complexity-Based Model where GE k =gate equivalent count for block k, e.g., estimated number of 2-input NANDs. GE k =gate equivalent count for block k, e.g., estimated number of 2-input NANDs. E typ =average energy consumed per clock cycle by an active typical 2-input NAND. E typ =average energy consumed per clock cycle by an active typical 2-input NAND. C Lk =average capacitance of a gate in block k. C Lk =average capacitance of a gate in block k. f =clock freqency. f =clock freqency. V DD =supply voltage. V DD =supply voltage. A k =average fraction of gates switching per cycle in block k. A k =average fraction of gates switching per cycle in block k. Power =ΣGE k (E typ + C Lk V DD 2 ) f A k All functional blocks k Ref.: K. Müller-Glaser, K. Kirsch and K. Neusinger, “Estimating Essential Design Characteristics to Support Project Planning for ASIC Design Management,” Proc. IEEE Int. Conf. CAD, Nov. 1991, pp

Copyright Agrawal, 2007ELEC6270 Spring 09, Lecture 75 Improving Complexity Models Treat logic, memory, interconnects and clock tree, separately. Treat logic, memory, interconnects and clock tree, separately. For example, a memory array may not be modeled as equivalent NAND gates, but as memory cells. For example, a memory array may not be modeled as equivalent NAND gates, but as memory cells.

Copyright Agrawal, 2007ELEC6270 Spring 09, Lecture 76 Memory array An On-Chip SRAM Sense and column decode Row decode and drivers Ctrl Address bus... Address bus word line bit line Six-transistor memory cell 2 k cells 2 n-k cells Data

Copyright Agrawal, 2007ELEC6270 Spring 09, Lecture 77 Power Consumed by SRAM 2 k Power = ── (c int l col + 2 n-k c tr ) V DD V swing f 2 Where2 k number of cells in a row c int wire capacitance per unit length l col memory column length 2 n-k number of cells in a column c tr minimum size transistor drain capacitance V swing bitline voltage swing Ref.: D. Liu and C. Svenson, “Power Consumption Estimation in CMOS VLSI Chips,” IEEE J. Solid-State Circuits, June 1991, pp

Copyright Agrawal, 2007ELEC6270 Spring 09, Lecture 78 Activity-Based Models Powerαcapacitance × activity Powerαcapacitance × activity Capacitanceα area Capacitanceα area Both area and activity can be estimated from the entropy of a Boolean function. Both area and activity can be estimated from the entropy of a Boolean function. Definition: Entropy of a system with m states having probabilities p1, p2,..., pm, is Definition: Entropy of a system with m states having probabilities p1, p2,..., pm, is m H= – Σ pk log 2 pkbits k=1

Copyright Agrawal, 2007ELEC6270 Spring 09, Lecture 79 Binary Signals Entropy of a binary signal: Entropy of a binary signal: H(p1) = – p1 log 2 p1 – (1– p1) log 2 (1– p1) H(p1) = – p1 log 2 p1 – (1– p1) log 2 (1– p1) Entropy of an n-bit binary vector: Entropy of an n-bit binary vector:n H(X)=ΣH(p1k) k=1 k=1

Copyright Agrawal, 2007ELEC6270 Spring 09, Lecture 710 Entropy and Activity p1k Entropy 4 p1k(1-p1k)

Copyright Agrawal, 2007ELEC6270 Spring 09, Lecture 711 Entropy of a Circuit Combinational Logic X1 X2 Xn Y1 Y2 Ym

Copyright Agrawal, 2007ELEC6270 Spring 09, Lecture 712 Input and Output Entropy 2 n Hi= –Σpk log 2 pk k=1 where pk = probability of kth input vector 2 m Ho= –Σpj log 2 pj j=1 where pj = probability of jth output vector

Copyright Agrawal, 2007ELEC6270 Spring 09, Lecture 713 Average Acrivity Hi Ho Circuit depth → PIPO 2/3 Average entropy ≈ ─── (Hi + 2Ho) n+m Quadratic decay Hi ≥ Ho

Copyright Agrawal, 2007ELEC6270 Spring 09, Lecture 714 Area Estimate K.-T. Cheng and V. D. Agrawal, “An Entropy Measure for the Complexity of Multi-Output Boolean Functions,” Proc. 17 th DAC, 1990, pp K.-T. Cheng and V. D. Agrawal, “An Entropy Measure for the Complexity of Multi-Output Boolean Functions,” Proc. 17 th DAC, 1990, pp M. Nemani and F. Najm, “Towards a High-Level Power Estimation Capability,” IEEE Trans. CAD, vol. 15, no. 6, pp , June M. Nemani and F. Najm, “Towards a High-Level Power Estimation Capability,” IEEE Trans. CAD, vol. 15, no. 6, pp , June Area=2 n Ho/nfor large n =2 n Hofor n ≤ 10

Copyright Agrawal, 2007ELEC6270 Spring 09, Lecture 715 Power N Power= K1 × Av. Activity ×Σ Ck = K2 × Av. Activity × Area k=1 where Ck is the capacitance of kth node in a circuit with N nodes 2 n+1 Power = K3 ────── Ho (Hi + 2Ho) 3n(n+m) Constant K3 is determined by simulation of gate-level circuits.

Copyright Agrawal, 2007ELEC6270 Spring 09, Lecture 716 Sequential Circuit Combinational Logic Flip-flops PIPO Hi Ho Hi and Ho are determined from high-level simulation.

Copyright Agrawal, 2007ELEC6270 Spring 09, Lecture 717 Empirical Methods Functional blocks are characterized for power consumption in active and inactive (standby) modes by Functional blocks are characterized for power consumption in active and inactive (standby) modes by Analytical methods, or Analytical methods, or Simulation, or Simulation, or Measurement Measurement A software simulator determines which blocks become active and adds their power consumption. A software simulator determines which blocks become active and adds their power consumption.

Copyright Agrawal, 2007ELEC6270 Spring 09, Lecture 718 Example: RISC Microprocessor IF ID EXMEM WB add R1← R2+R3 lw R4 ← 4(R5) Clock cycles mem rfile ALU rfile pcadd bradd memrfile ALU mem rfile pcaddbradd mem ALU rfile mem ALU rfile ALU rfile mem time Power profile

Copyright Agrawal, 2007ELEC6270 Spring 09, Lecture 719 Additional References P. E. Landman, “A Survey of High-Level Power Estimation Techniques,” in Low-Power CMOS Design, A. Chandrakasan and R. Brodersen (Editors), New York: IEEE Press, P. E. Landman, “A Survey of High-Level Power Estimation Techniques,” in Low-Power CMOS Design, A. Chandrakasan and R. Brodersen (Editors), New York: IEEE Press, P. E. Landman and J. M. Rabaey, “Activity- Sensitive Architectural Power Analysis,” IEEE Trans. CAD, vol. 15, no. 6, pp , June P. E. Landman and J. M. Rabaey, “Activity- Sensitive Architectural Power Analysis,” IEEE Trans. CAD, vol. 15, no. 6, pp , June A. Raghunathan, N. K. Jha, and S. Dey, High- level power analysis and optimization, Boston: Springer, A. Raghunathan, N. K. Jha, and S. Dey, High- level power analysis and optimization, Boston: Springer, 1997.