1. Low Power Design of Integrated Systems Assoc. Prof. Dimitrios Soudris dsoudris@ee.duth.gr

2. Technology Directions: SIA Roadmap

3. Technology Process Evolution Technology Directions: SIA Roadmap 2002

4. Transistors #Transistors

5. Frequency

6. Performance

7. Power Consumption Power consumption

8. Supply Voltage Scaling

10. Power Terminology Power is the rate at which energy is delivered or exchanged » electrical energy is converted to heat energy during operation Power Dissipation - rate at which energy is taken from the source (V dd ) and converted into heat

11. Why Smaller Power? Large Market of Portable devices –e.g. laptops, mobile phones Achieve larger transistor integration –Pentium IV contains 42 million transistors –Teraflops chip contains 1.9 billion transistors Need for “green” computers –10% of total electrical energy consumed by PCs

12. Battery Technology Improvements

13. The Industry’s Reaction Reduce chip capacitance through process scaling ==> Expensive Reduce Voltage levels from 5V  3.3V  2V ==> Industry is hard to move (microprocessors, memory,...) Better Circuit Techniques ==> Gated clocks, Power-Down of non-operational units… Example: IBM 80 MHz PowerPC RISC (3 W @ 3.3V) –Power Management Logic determines activity on per cycle basis –Clocks of idle blocks are turned off  12-30% savings –Doze - Nap and Sleep mode (5 mW)

14. Example: Intel Pentium-II processor Pentium-1: 15 Watt (5V - 66MHz) Pentium-2: 8 Watt (3.3V- 133 MHz)

15. Where Does Power Go in CMOS? The power consumption in digital CMOS circuits P avg = P dynamic + Pshort-circuit + P leakage Dynamic Power Consumption Short Circuit Currents Leakage (Static) Charging and Discharging Capacitors Short Circuit Path between Supply Rails during Switching Leaking diodes and transistors

16. Present & Future in Power Consumption

17. Dynamic Power Consumption(1) where V DD supply voltage, C L capacitance, N is the average number of transitions per clock cycle, and f frequency operation

18. For technologies up to 0.35  m, the dynamic consumption is about 80% of the total consumption Goal ===> reduce dynamic power consumption –reduction capacitance –reduction of supply voltage –reduction of frequency –reduction of switching activity –or combination of above factors Dynamic Power Consumption (2)

19. Leakage current consumption the reverse-bias diode leakage at the transistor drains and the sub-threshold current through an turned-off transistor channel

21. The Design Flow

22. Power savings in terms of the design level

23. Lower V dd Increases Delay

24. Reducing V dd

25. Lowering the Threshold

26. Transistor Sizing for Power Minimization

27. Techniques to reduce supply voltage

28. Techniques to minimizing the switched capacitance

29. Power consumption of transfer and storage over datapath operations both in hardware [Men95] and software [Tiw94, Gon96].

30. Architecture Power Optimization Techniques Architecture-driven voltage reduction: The key idea is to speed up the circuit in order to be able reduces voltage while meeting throughput rate constraints. Voltage reduction can be achieved by introducing parallelism in hardware or inserting flip-flops Switching activity minimization: Try to prevent the generation and propagation of spurious transitions or to reduce the number of transitions, e.g. retiming, path balancing, data representation Switched capacitance minimization: Aim at the minimization of switched capacitance Dynamic power management: Under certain conditions, a circuit part becomes inactive, avoiding unnecessary calculations, e.g. gated clocks, operand isolation, pre- computation, and guarded evaluation

31. Architecture Trade-offs: Reference Data Path Critical path delay  T adder + T comparator (= 25ns),  f ref = 40MHz Total capacitance being switched = C ref V dd = V ref = 5V Power for reference datapath = P ref = C ref V ref 2 f ref

32. Voltage Reduction Technique: Parallelism The clock rate can be reduced by half with the same throughput  f par = f ref / 2 V par = V ref / 1.7 C par = 2.15 C ref P par = (2.15 C ref ) (V ref /1.7) 2 (f ref /2)  0.36 P ref

33. Voltage Reduction Technique: Pipeline f pipe = f ref, C pipe = 1.1 C ref, V pipe = V ref /1.7 Voltage can be dropped while maintaining the original throughput P pipe = C pipe V pipe 2 f pipe = (1.1 C ref ) (V ref /1.7) 2 f ref = 0.37 P ref

34. Comparisons

35. Logic Style and Power Consumption Power-delay product improves as voltage decreases The “best” logic style minimizes power-delay for a given delay constraint

36. The concept of gating clock signals

37. Resource Sharing Can Increase Activity

38. Reducing Effective Capacitance

39. Data representation Sign-extension activity significantly reduced using sign-magnitude representation

40. Switching Activity in Adders

41. Switching Activity in Multipliers

42. Signals and Operations Reordering Example: complex multiplication Trading a multiplication for an addition

43. Module Selection

44. Glitching activity reduction (3)

45. Two-Level Logic Circuits Switching Activity Minimization (1) Taking into account the static and transition probabilities (i.e. temporal correlation) of the primary inputs, we can insert in certain gates of the first logic level (i.e. AND gates), additional input signals resulting into reduced switching activity Appropriately-selected input signals force the outputs of the AND gates to logic level zero for a number of combinations of the binary input signals

46. Two-Level Logic Circuits Switching Activity Minimization (2) Example: Signal x 3 exhibits low-transition probability and high static-1 probability, while the signals x 0, x 1, and x 2 are characterized by high-transition probabilities

47. A. Chandrakasan and R. Brodersen, “Low Power CMOS Design”, Kluwer Academic Publishers, 1995 Christian Piguet, Editor, « Low-Power Electronics Design”, CRC Press, November 2004 D. Soudris, C. Piguet, C. Goutis, “Designing CMOS Circuits for Low- Power”, Kluwer Academic Press, October 2002 F. Catthoor, K. Danckaert, et. al.: 2002, Data Access and Storage Management for Embedded Programmable Processors. Kluwer Academic Publishers Stamatis Vassiliadis and Dimitrios Soudris, “Fine- and Coarse- Grain Reconfigurable Computing” Springer, Dordrecht/London/Boston, August 2007 http://vlsi.ee.duth.gr/~dsoudris AMDREL website  http://vlsi.ee.duh.gr/amdrel Additional Info