1. 11/2-4/04ELEC 5970-003/6970-0031 ELEC 5970-003/6970-003 (Fall 2004) Advanced Topics in Electrical Engineering Designing VLSI for Low-Power and Self-Test Estimating Power Consumption Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu

2. 11/2-4/04ELEC 5970-003/6970-0032 Power Estimation Techniques Logic simulation Circuit-level simulation Probabilistic estimation Peak power estimation Power estimation for a high-level design

3. 11/2-4/04ELEC 5970-003/6970-0033 CaCa Logic Model of a CMOS Circuit CcCc CbCb V DD a b c pMOS FETs nMOS FETs C a, C b and C c are parasitic capacitances DcDc DaDa c a b D a and D b are interconnect or propagation delays D c is inertial delay of gate DbDb

4. 11/2-4/04ELEC 5970-003/6970-0034 Options for Inertial Delay (simulation of a NAND gate) b a c (CMOS) Time units 0 5 c (zero delay) c (unit delay) c (multiple delay) c (minmax delay) Inputs Logic simulation min =2, max =5 rise=5, fall=5 Transient region Unknown (X) X

5. 11/2-4/04ELEC 5970-003/6970-0035 Signal States Two-states (0, 1) can be used for purely combinational logic with zero-delay. Three-states (0, 1, X) are essential for timing hazards and for sequential logic initialization. Four-states (0, 1, X, Z) are essential for MOS devices. See example below. Analog signals are used for exact timing of digital logic and for analog circuits. 0 0 Z (hold previous value)

6. 11/2-4/04ELEC 5970-003/6970-0036 True-Value Simulation Algorithm Event-driven simulation Only gates or modules with input events are evaluated (event means a signal change) Gate and interconnect delays are used to determine the transients at gate outputs Per-vector complexity of computation is linear in number of gates × total input to output time delay units

7. 11/2-4/04ELEC 5970-003/6970-0037 Event-Driven Algorithm Example 2 2 4 2 a =1 b =1 c =1→0 d = 0 e =1 f =0 g =1 Time, t 0 4 8 g t = 0 1 2 3 4 5 6 7 8 Scheduled events c = 0 d = 1, e = 0 g = 0 f = 1 g = 1 Activity list d, e f, g g Time stack

8. 11/2-4/04ELEC 5970-003/6970-0038 Time Wheel (Circular Stack) t=0 1 2 3 4 5 6 7 max Current time pointer Event link-list

9. 11/2-4/04ELEC 5970-003/6970-0039 Power Estimation For every vector (changes at primary input): –At every signal node (gate output): Count number of transitions Compute #transitions × node capacitance × VDD 2 /2 If node capacitances are not known, use fanout approximation – often used for relative power comparison between circuits Add pre-estimated leakage power for vector period

10. 11/2-4/04ELEC 5970-003/6970-00310 PowerMill: A Power Estimator Event-driven simulator Switch-level simulation with delays 2-3 orders of magnitude faster than Spice Estimates power for given vectors, due to –Instantaneous, average and rms currents –Steady-state transitions and glitches –Short-circuit and leakage currents

11. 11/2-4/04ELEC 5970-003/6970-00311 PowerMill (Cont.) Determines current density and voltage drop in the power net Points to potential problem areas on a VLSI chip for EM failures, ground bounce, excessive voltage drop, heating Reference: C. Deng, “Power Analysis for CMOS/BiCMOS Circuits,” Proc. International Workshop on Low Power Design, April 1994, pp. 3-8.

12. 11/2-4/04ELEC 5970-003/6970-00312 Switch-Level Simulation 1 1 1 0 1 1 ? R. E. Bryant, “A Survey of Switch-Level Algorithms,” IEEE Design & Test of Computers, vol. 4, no. 4, pp. 26-40, August 1987. Channel-connected components

13. 11/2-4/04ELEC 5970-003/6970-00313 Entice-Aspen: Gate-level Tool Gate-level circuit is partitioned into cells. Cells are simulated in Spice for power dissipation for all possible input events. Logic simulation determines the events at cell inputs, adding the corresponding power dissipated by each cell. B. J. George, D. Gossain, S. C. Tyler, M. G. Wloka, and G. K. H. Yeap, “Power Analysis and Characterization for Semi-Custom Design,” Proc. International Workshop on Low Power Design, April 1994, pp. 215-218.

14. 11/2-4/04ELEC 5970-003/6970-00314 RTL Power Estimation Two step procedure: –Behavioral simulation to collect the input statistics for all modules in RTL description –Develop power macro-model for each module and sum the power Q. Wu, C.-S. Ding, C.-T. Hsieh, and M. Pedram, “Statistical Design of Macro- Models for RT-Level Power Estimation,” Proc. Second Asia-Pacific Design Automation Conference, Jan. 1997.

15. 11/2-4/04ELEC 5970-003/6970-00315 Behavioral Activity Simulation Module description is modified to collect input statistics. Example: 16-bit multiplier module c = a*b; r1 = a^a’; r2 = b^b’; for (i=0; i <16; i++ ) { sw_a[ i ] += r1 & 1; sw_b[ i ] += r2 & 1; r1 = r1 >> 1; r2 = r2 >> 1; } a’ = a; b’ = b;

16. 11/2-4/04ELEC 5970-003/6970-00316 Power Macro-Model Develop analytic models for estimating the switched capacitance as a function of circuit complexity and technology/library parameters. OR Synthesize the circuit and then estimate power dissipation by simulation with random vectors. Both methods determine effective switched capacitance per input transition.

17. 11/2-4/04ELEC 5970-003/6970-00317 Effective Switched Capacitance where –V is supply voltage – f is vector frequency –C is effective switched capacitance/input transition –E is input activity (bit changes) per vector Power dissipation of a module = 0.5 V 2 f C E

18. 11/2-4/04ELEC 5970-003/6970-00318 Probabilistic Methods Signal probability: Expected value of a binary signal, s E(s)= lim (1/T) ∫ s(t) dt = Prob(s=1) = p(s) =1.p(s) + 0.(1-p(s)) t=0 T

19. 11/2-4/04ELEC 5970-003/6970-00319 Switching Probability psw(s(t))= p(s(t-ε))(1-p(s(t))) + (1-p(s(t-ε)))p(s(t)) =p(s(t-ε)) + p(s(t)) – 2p(s(t-ε))p(s(t)) If p(s(t-ε)) = p(s(t)) = p(s), then psw(s(t))=2p(s)(1-p(s)) Dynamic power= 0.5 CV DD 2 psw(s(t)) f

20. 11/2-4/04ELEC 5970-003/6970-00320 Uncorrelated Signals NOT: c = a, p(c) = 1 – p(a) AND: c = ab, p(c) = p(a)p(b) OR: c = a+b, p(c) = 1 - (1-p(a))(1-p(b)) = p(a) + p(b) – p(a)p(b)

21. 11/2-4/04ELEC 5970-003/6970-00321 Correlated Signal Example p(a) = 0.5 p(c) = 0.5 p(b) = 0.5 0.5 0.25 0.25+0.25-0.0625 = 0.4375 Switching probability psw(output) = 2×0.4375×(1-0.4375) = 0.4921875 output

22. 11/2-4/04ELEC 5970-003/6970-00322 Correlated Signals (Corrected) abcoutputProb. 00000.125 0010 0101 0110 1000 1011 1101 1111 p(output) = 0.5 psw(output) = 2×0.5×0.5 = 0.5

23. 11/2-4/04ELEC 5970-003/6970-00323 Symbolic Analysis p(a) = 0.5 p(c) = 0.5 p(b) = 0.5 1-p(c) = 0.5 p(a)p(c) = 0.25 p(b)(1-p(c)) = 0.25 0.25+0.25-0.0625 = 0.4375 p(a)p(c) + p(b)(1-p(c)) - p(a)p(b)p(c)(1-p(c)) =p(a)p(c)+p(b)-p(b)p(c) = 0.5 K. P. Parker and E. J. McCluskey, Probabilistic Treatment of General Combinational Networks,” IEEE Trans. Computers, vol. C-24, no. 6, pp. 668-670, June 1975. output

24. 11/2-4/04ELEC 5970-003/6970-00324 Supergate S. C. Seth and V. D. Agrawal, “A New Method for Computation of Probabilistic Testability in Combinational Circuits,” Integration, the VLSI Journal, vol. 7, no. 1, pp. 49-75, April 1989. b output a c Supergate of a signal is the smallest circuit partition including all fanout stems dominated by that signal. Supergate(output)

25. 11/2-4/04ELEC 5970-003/6970-00325 PREDICT Algorithm To calculate p(output), enumerate signal states at fanout signal(s) – c in this example. For each case i, compute p i (output) separately. Compute p(output) = p(c)p 1 (output) + (1-p(c))p 0 (output)

26. 11/2-4/04ELEC 5970-003/6970-00326 Supergate Example p (b)=0.5 output p(a)=0.5 c=0 1 0.0 0.5 p (b)=0.5 output p(a)=0.5 c=1 0 0.5 0.0 0.5 P(output) = p(c) 0.5 + (1-p(c)) 0.5 = 0.5

27. 11/2-4/04ELEC 5970-003/6970-00327 Other Signal Probability Methods Weighted averaging –B. Krishnamurthy and I. G. Tollis, “Improved Techniques for Estimating Signal Probabilities,” IEEE Trans. Computers, vol. C- 38, no. 7, pp. 1245-1251, July 1989. Cutting algorithm –J. Savir, G. Ditlow and P. Bardell, “Random Pattern Testability,” IEEE Trans. Computers, vol. C-33, no. 1, pp. 79-90, Jan. 1989. OBDD –R. E. Bryant, “Graph-Based Algorithms for Boolean Function Manipulation,” IEEE Trans. Computers, vol. C-35, no. 8, pp. 677- 691, Aug. 1989. Transition density –F. N. Najm, “Transition Density: A New Measure of Activity in Digital Circuits,” IEEE Trans. CAD, vol. 12, no. 2, pp. 310-323, Feb. 1993.

28. 11/2-4/04ELEC 5970-003/6970-00328 Working with Delays Signal probability methods do not take delays into account. Hence, glitch power is not included. Timed symbolic simulation –A Ghosh, S. Devadas, K. Keutzer and J. White, “Estimation of Average Switching Activity in Combinational and Sequential Circuits,” Proc. 29 th Design Automation Conf., June 1992, pp. 253-259. Probability waveform simulation –C.-S. Ding, C.-Y. Tsui and M. Pedram, “Gate-Level Power Estimation Using Tagged Probabilistic Simulation,” IEEE Trans. CAD, vol. 17, no. 11, pp. 1099-1107, Nov. 1998.