©2006 Avanex, Inc. All rights reserved. CONFIDENTIALITY NOTICE: The information contained in this presentation is Avanex confidential information. Any.

Slides:

Advertisements

Similar presentations

RAD Engineering BLM VME J2 Backplane Printed Circuit Board Backplane Crosstalk Comparison January 25, 2005.

Advertisements

Specific requirements for analog electronics of a high counting rate TRD Vasile Catanescu NIHAM - Bucharest CBM 10th Collaboration Meeting Sept 25 – 28,

Test of LLRF at SPARC Marco Bellaveglia INFN – LNF Reporting for:

M.J. LeVine1STAR HFT meeting, Sept 27-28, 2011 STAR SSD readout upgrade M. LeVine, R. Scheetz -- BNL Ch. Renard, S. Bouvier -- Subatech J. Thomas -- LBNL.

FPGA PID Heater/Cooler Controller Galt Design, Inc.

RPC Electronics Status Overall system TDC –Digitizing frequency issue (determine the bin size of the TDC value) Discriminator test result Trigger module.

Gwynneth Davidoff, Kendall Pletcher, Mary Schmidt, Amy Whitcombe.

1 FINAL PRESENTATION PART A Implementation of generic interface To electronic components via USB2 Connection Supervisor Daniel Alkalay System architectures.

High Speed, high common mode immunity communication interface Team May12-05 Chendong Yang Mengfei Xu Advisor: Nathan Neihart Client: RBC Medical Development.

Timepix2 power pulsing and future developments X. Llopart 17 th March 2011.

©Alex Doboli Chapter 3: Hardware and Software Subsystems of Mixed-Signal Architectures (Part II) Alex Doboli, Ph.D. Department of Electrical and Computer.

Viking Pump Flow Manager - Phase 2 Senior Design May

Mathieu Goffe EUDET JRA1 meeting, DESY Wednesday 30 January 2008 IPHC, 23 rue du Loess BP 28, 67037, Strasbourg Cedex 02, France.

Development of a 20 GS/s Sampling Chip in 130nm CMOS Technology Jean-Francois Genat On behalf of Mircea Bogdan 1, Henry J. Frisch 1, Herve Grabas 3, Mary.

Diffuse Optical Tomography Optimization and Miniaturization ECE 4902-Spring 2014 Thomas Capuano (EE&BME), Donald McMenemy (EE), David Miller (EE), Dhinakaran.

1 Warsaw University of Technology Faculty of Electronics and Information Technology Institute of Electronic Systems HARDWARE SIMULATOR of the high-resolution.

Electronics for PS and LHC transformers Grzegorz Kasprowicz Supervisor: David Belohrad AB-BDI-PI Technical student report.

Trigger Supervisor (TS) J. William Gu Data Acquisition Group 1.TS position in the system 2.First prototype TS 3.TS functions 4.TS test status.

Kris Blair Nathan Edwards Jonathan Lindsay Daniel Moberly Jacob Rosenthal CUbiC Advisors: Sreekar Krishna and Troy McDaniel Wireless Haptic Belt Preliminary.

1HSSPG Georgia Tech High Speed Image Acquisition System for Focal-Plane-Arrays Doctoral Dissertation Presentation by Youngjoong Joo School of Electrical.

High Speed Data Converter University

DLS Digital Controller Tony Dobbing Head of Power Supplies Group.

LSST Electronics Review – BNL, January LSST Electronics Review BNL January Power & Voltage Plan R. Van Berg Electronics Mini-Review.

H IGH S PEED, HIGH COMMON MODE IMMUNITY COMMUNICATION INTERFACE Team May12-05 Chendong Yang Mengfei Xu Advisor: Nathan Neihart Client: RBC Medical Development.

CARIOCA (Cern and RIO Current Amplifier). The CARIOCA chip has 8 binary output, therefore DIALOG has 16 PCH as input channels and has up to 8 LCH as output.

©2008 Avanex, Inc. All rights reserved.1 WISDOM bi-quaterly meeting Cork, Ireland Intelligent Photonic Solutions ™ F.Doukhan F.Dinallo M.Omar January 15th,

THEMIS Instrument CDR 1 UCB, April 19-20, 2004 Boom Electronics Board (BEB) Engineering Peer Review Apr. 20, 2004 Hilary Richard.

SNS Integrated Control System Timing Clients at SNS DH Thompson Epics Spring 2003.

CCD Cameras with USB2.0 & Gigabit interfaces for the Pi of The Sky Project Grzegorz Kasprowicz Piotr Sitek PERG In cooperation with Soltan Institute.

Features of the new Alibava firmware: 1. Universal for laboratory use (readout of stand-alone detector via USB interface) and for the telescope readout.

©2006 Avanex, Inc. All rights reserved. CONFIDENTIALITY NOTICE: The information contained in this presentation is Avanex confidential information. Any.

ATLAS ATLAS DCS B.Hallgren, CERN EP/ ATI PRR CERN 4 March the Embedded Local Monitor Board ELMB Design description of the Embedded Local Monitor.

Lecture 16: Digital to Analog Converter - PWM Implementation

RTL Hardware Design by P. Chu Chapter Poor design practice and remedy 2. More counters 3. Register as fast temporary storage 4. Pipelined circuit.

Timing Requirements for Spallation Neutron Sources Timing system clock synchronized to the storage ring’s revolution frequency. –LANSCE: MHz.

Alexei SemenovGeneric Digitizer Generic Digitizer 10MHZ 16 bit 6U VME Board.

NUMI Off Axis NUMI Off Axis Workshop Workshop Argonne Meeting Electronics for RPCs Gary Drake, Charlie Nelson Apr. 25, 2003 p. 1.

WP5 – Wirespeed Photonic Firewall Validation Start M27, finish M35 Avanex lead Description of Work –Establish test bed suitable to validated the optical.

Charge Measurement Using Commercial Devices Jinyuan Wu, Zonghan Shi For CKM Collaboration. Jan

CSE 171 Lab 11 Digital Voltmeter.

ESS Timing System Prototype 2012 Miha Reščič, ICS

Sophie BARON, PH-ESSLEADE, 15/06/06 1 TTC upgrade Status May 2006  Overview  AB/RF optical links  Receiver crate  Status and schedules  Documentation.

WISDOM WP6 Manufacturability, Scalability and Functionality Study Start M0, End M35 WP leader is CIP Objectives –Assessment of manufacturability of the.

S. Bota – Calorimeter Electronics overview - July 2002 Status of SPD electronics Very Front End Review of ASIC runs What’s new: RUN 4 and 5 Next Actions.

WP5 – Wirespeed Photonic Firewall Validation Start M27, finish M41(tbc) CIP now lead Description of Work –Establish test bed suitable to validated the.

Tobias Stadlbauer Special Magnets MedAustron 7-8 October 2010 Special Magnets Controls Status and Plans IntroductionPower SupplySlow ControlsAOB.

Closed Loop Temperature Control Circuit with LCD Display Mike Wooldridge ECE 4330 Embedded Systems.

RTL Hardware Design by P. Chu Chapter 9 – ECE420 (CSUN) Mirzaei 1 Sequential Circuit Design: Practice Shahnam Mirzaei, PhD Spring 2016 California State.

Visible Light Photon Counter Integrator Group 48: Katie Nguyen, Austin Jin ECE445 Spring 2016 May 1, 2016.

WISDOM Demonstrator End of project experiment to demonstrate optical security checking Hardware/software for TCP port checking Proposal –Use software defined.

Programmable Power Supply Characterization presentation Dec. 04, 2007 Gregory Kaplan Dmitry Babin Supervisor: Boaz Mizrahi.

Infrared Transmitter and Receiver Block Design

LHCb Outer Tracker Electronics 40MHz Upgrade

DAQ ACQUISITION FOR THE dE/dX DETECTOR

RF section Control section Output Section Df Df Df CPU Hybrid LC

Calorimeter Mu2e Development electronics Front-end Review

Microcontroller Applications

Workshop on INTRODUCTION OF MATLAB/SIMULINK TOOLS AND THEIR APPLICATION conducted by EEE/CCET 11/13/2018 workshop on 01/12/2010.

Master I/O Connectors PL12 PL14 PL21 PL20 PL17.

CSE 171 Lab 11 Digital Voltmeter.

AQT90 FLEX Service Training

HallD Collaboration Meeting Jefferson Lab December 11-13, 2003

CrystaLatchTM High Power 1x1,1x2 Solid-State Fiberoptic Switch (5W CW)

Optical Switch Evaluation Kit Circuit Board and Software (ROHS6-MB01A)

Performance Specifications

CrystaLatchTM 1x1, 1x2, Solid-State Fiberoptic Switch

Optical Switch Evaluation Kit Circuit Board and Software

CrystaLatchTM Bi-Directional 1x1,1x2 Solid-State Fiberoptic Switch

Optical Switch Evaluation Kit Circuit Board and Software (ROHS6-MB01B)

DC-20KHz Driver for NanoSpeedTM VOA (patents pending)

Presentation transcript:

©2006 Avanex, Inc. All rights reserved. CONFIDENTIALITY NOTICE: The information contained in this presentation is Avanex confidential information. Any dissemination, distribution or copying of this presentation or disclosure of the information contained within by any unauthorized person is strictly prohibited. WISDOM PROJECT 12/19/07 PLAN FOR SECOND YEAR WORK TEST PLATFORM HW DESIGN

©2006 Avanex, Inc. All rights reserved. CONFIDENTIALITY NOTICE: The information contained in this presentation is Avanex confidential information. Any dissemination, distribution or copying of this presentation or disclosure of the information contained within by any unauthorized person is strictly prohibited. 2 WISDOM Y02 PLAN  AVANEX planned contribution in WISDOM project Y02 is in WP4: optical processing sub-system development. With a more focus on electrical design and software control  Contribute to finalize architecture of the control electronic requirement By Optimizing the number of block to design By Offering a scalable architecture By defining proper control structure  Finalize the electronic requirement Specify each electrical block to develop Specify each software block to develop  Provide test structure for evaluation and control

©2006 Avanex, Inc. All rights reserved. CONFIDENTIALITY NOTICE: The information contained in this presentation is Avanex confidential information. Any dissemination, distribution or copying of this presentation or disclosure of the information contained within by any unauthorized person is strictly prohibited. 3 Platform Approach  Use of a single PCB platform design to drive different building blocks MZI Switch Optional pattern generator  One PCB can drive 2 independent switch/MZI  Configuration done by HW selection  Settings loaded using configuration files GUI configured by HW PCBA configuration  GUI to configure as well functions (MZI/SW) as HW optics (SOA/Heater)  Use of USB interface to // boards (up to 10) Each board have separated configuration file Use of ECL technology to offer high speed and fast transient circuit – Use of shifted ECL interface to allow 50  direct DC load to GND

©2006 Avanex, Inc. All rights reserved. CONFIDENTIALITY NOTICE: The information contained in this presentation is Avanex confidential information. Any dissemination, distribution or copying of this presentation or disclosure of the information contained within by any unauthorized person is strictly prohibited. 4 SW interface

©2006 Avanex, Inc. All rights reserved. CONFIDENTIALITY NOTICE: The information contained in this presentation is Avanex confidential information. Any dissemination, distribution or copying of this presentation or disclosure of the information contained within by any unauthorized person is strictly prohibited. 5 MZI driver block 1/2 DAC ADC Heater Current Set Or Heater Voltage set HeaterCurrentSense HEATER DRIV ER HeaterVoltageSense Heater Enable/Disable status µC DAC ADC SOACurrentSetSOACurrentSet SOACurrentSe nse SOA DRIV ER SOAVoltageSe nse SOA Enable/Disable status

©2006 Avanex, Inc. All rights reserved. CONFIDENTIALITY NOTICE: The information contained in this presentation is Avanex confidential information. Any dissemination, distribution or copying of this presentation or disclosure of the information contained within by any unauthorized person is strictly prohibited. 6 MZI driver block 2/2 µC DRIV ER DAC ADC Pe lti er Cu rr en tS et PeltierCurrentSense Peltier Rth Analog_Peltier _ TempSens e PeltierVoltageSense T e m p er at ur e _ S et PID Digital_Peltier _ TempSens e TEC Enable/Disable status

©2006 Avanex, Inc. All rights reserved. CONFIDENTIALITY NOTICE: The information contained in this presentation is Avanex confidential information. Any dissemination, distribution or copying of this presentation or disclosure of the information contained within by any unauthorized person is strictly prohibited. 7 Switch Block µC DAC ADC SOACurrentSetSOACurrentSet SOACurrentSe ns e SOA DRIV ER SOAVoltageSe nse SOA Enable/Disable status Re sist or 50 Oh ms RF ECL input shifted, DC coupled µC DRI VER DAC ADC P el ti e r C u rr e n t S et PeltierCurrentSense Peltier Rth Analog_Peltier _ TempS ense PeltierVoltageSense Temperature_SetTemperature_Set PID Digital_Peltier _ TempS ense TEC Enable/Disable status

©2006 Avanex, Inc. All rights reserved. CONFIDENTIALITY NOTICE: The information contained in this presentation is Avanex confidential information. Any dissemination, distribution or copying of this presentation or disclosure of the information contained within by any unauthorized person is strictly prohibited. 8 Pattern generator block Target pattern DC coupled < 200 MHZ 8 /16/ 32 bits circular registers & electronic control Pattern triger < 200 MHZ µC Delayed initialising pulse DC coulped < 200 MHZ Driver Electronic system control EC L OU TP UT TE CH NO LO GY SH IF TE D Target bit rate AC couoled ; Vpp = 500 mv Load target N bits Delayed Reset pulse DC coulped < 200 MHZ Delayed Output gate DC coulped < 200 MHZ Delayed Input data select control DC coulped < 200 MHZ