Presentation is loading. Please wait.

Presentation is loading. Please wait.

HallD Collaboration Meeting Jefferson Lab December 11-13, 2003

Similar presentations


Presentation on theme: "HallD Collaboration Meeting Jefferson Lab December 11-13, 2003"— Presentation transcript:

1 HallD Collaboration Meeting Jefferson Lab December 11-13, 2003
R. Chris Cuevas Physics Division Group Leader -- Fast Electronics Recent Activities: F1-TDC Production News VME Discriminator/Scaler Module 4/21/2019 Hall D Collaboration, December R.C. Cuevas

2 Hall D Collaboration, December 2003 --R.C. Cuevas
F1TDC Production Progress Order placed for fifty (50) modules in September 2003 Contract awarded to Catalyst Manufacturing, Inc. Site visit on November 6th, 2003 4/21/2019 Hall D Collaboration, December R.C. Cuevas

3 Hall D Collaboration, December 2003 --R.C. Cuevas
F1TDC Production Progress Site Visit Photos 6-Nov-2003 4/21/2019 Hall D Collaboration, December R.C. Cuevas

4 Hall D Collaboration, December 2003 --R.C. Cuevas
4/21/2019 Hall D Collaboration, December R.C. Cuevas

5 Hall D Collaboration, December 2003 --R.C. Cuevas
F1TDC Test Details Two 1st Article Boards will be inspected and tested thoroughly After JLAB approval, remaining 48 boards will be assembled Test ‘station’ has been prepared. FPGA code will have to be loaded on each board. DAQ routines are established and will provide functional testing for each production board. Full crate testing and multi module [Block Read] testing will also be performed. F1 will require further testing before loading on-board EEPROM with final initialization data. 4/21/2019 Hall D Collaboration, December R.C. Cuevas

6 VME Discriminator/Scaler
‘New Product’ VME Discriminator/Scaler 4/21/2019 Hall D Collaboration, December R.C. Cuevas

7 Hall D Collaboration, December 2003 --R.C. Cuevas
4/21/2019 Hall D Collaboration, December R.C. Cuevas

8 VME Discriminator/Scaler Specification Highlights
16 Coaxial Analog Inputs -- DC coupled -- +/-2.5V Ohm Termination VME Programmable Threshold [Common] Bit DAC VME Programmable Pulse Width -- 8nS to 100nS VME Programmable Delay [ Discriminator Output ] 0nS to 250nS -- 8nS step size 2 Scaler Gates -- NIM level 2 scalers per discriminator channel used with Gate1 and Gate2 32 bit scaler width Analog multiplexer -- 1:16 -- VME control to monitor analog input signal Discriminator Output --> Differential ECL on standard 17 pair cable to TDC Read Registers for all voltages and temperature of module Single width 6U VME module format 4/21/2019 Hall D Collaboration, December R.C. Cuevas


Download ppt "HallD Collaboration Meeting Jefferson Lab December 11-13, 2003"

Similar presentations


Ads by Google