1. LSST Electronics Review – BNL, January 25-26 20121 LSST Electronics Review BNL January 25-26 2012 Power & Voltage Plan R. Van Berg Electronics Mini-Review January 26 th, 2012

2. LSST Electronics Review – BNL, January 25-26 20122 Outline – Power Supplies for the RTMs Overview – Power Distribution System Power needs –FEB –RCC Vendor specific voltages –ITL –E2V Sequencing Protection

3. LSST Electronics Review – BNL, January 25-26 20123 Estimated Power Needs (LCA-275) – Science Rafts Peak Total Power (W) Sub-Assembly / ComponentQtyPower/ UnitPeak PowerQuiet PowerDuty CycleAvg Power Sci Raft Sensor Ass'y (RSA) 102.6 1.40 144.1 CCD's 66.0 53.7 Clock power1890.07313.80.00 1/91.5 Output Amp power1890.27652.2 1.052.2 Raft Plate trim heaters211.74636.70.01.036.7 Sci Front End Board (FEB) 564.8 0.67 380.6 ASPIC3780.20075.63.0 1/911.1 SCC5670.593336.0225.0 1/9237.3 CCD Current Source30240.042127.0 1.0127.0 Regulators1260.20826.22.5 1/95.2 Sci Raft Ctl Crate (RCC) 858.6 0.49 416.5 Back End Board (BEB) 732.6 290.5 ADCs30240.00515.10.151 1/91.8 Diff Amps30240.128387.136.3 1/975.3 Power regulators1150.000280.0 163.0 CPLD etc.1260.40050.40.01.050.4 Raft Control Module (RCM) 126.0 Raft Control Module board216.000126.00.01.0126.0

4. LSST Electronics Review – BNL, January 25-26 20124 Power Control & Monitoring – Design Concept for the Power Distribution System (PDS) Commercial AC components (filters, distribution) Commercial AC  48V converter Custom, isolated, 48V  DC converters for each load (rafts, HCUs, others) – full monitoring of I & V for each load Individual control of each load Located outside cryostat in UT Accessible during day Power fed through flange Independent supply each RTM

5. LSST Electronics Review – BNL, January 25-26 20125 Power Distribution System Location – Cabling Route Crates house support electronics in the Utility Trunk – in a volume that can be accessed within a single day shift for field replacement –Power regulators – custom and commercial –Opto converters –Timing and control fanout –Network switch(es) –Hardware Control Units (small computers) for CCS –Dedicated controllers (gauges, motors,…) Cabling harnesses and single cables –Cryostat to Crates – Raft power, data, timing –Sensors and operators in UT and CB to crates – power, control

6. LSST Electronics Review – BNL, January 25-26 20126 Raft Power Card Powers one to three RTMs (TBD) DC-DC converters to go from 48V DC “mains” to required levels Additional level of linear regulation in PDS for all sensitive voltages Each supply for each RTM is independent with independent supply and return lines (control is via isolated connections) Typical voltages – (note this is at less than 30W per FEC + 20W per RCC average power) –+7V for analog on FEB (one more linear regulation stage on FEB) – becomes +5V –+7V for CABAC on FEB – becomes +5V –+7V for digital on BEB / RCM – becomes +5; +3.5; +2.5; +1.8V –+35V for biases (CABAC) – adjusted on BEB –+12V for clock high levels (CABAC) adjusted on BEB –-70V for CCD substrate bias (e2V version) only adjusted at PDS

7. LSST Electronics Review – BNL, January 25-26 20127 7 CCD Voltage Requirements OD & Biasese2v CCD250ITL/STA1920AHPK S10892-03 exposereadouterase Back substrateBS-70BB-10VBB50300,2 Front substrateFS0SUB0VGR000 GuardGD30SC16---- Output DrainVOD30OD27VOD-5-20-5 Output GateVOG2OG-2VOG-5 Reset DrainVRD18RD15VRD-5-12-5 Test inject source----VISV-5-12-5 Test inject gate----VIGV000 ClocksHILOHILOHILO erase Parallel904-11-53 6 Serial100,54-4-63 6 Reset Gate9010-2-65 Summing Well--4-4-65 Transfer Gate-----53 Capacitances (estimated) Parallel per phase64nFunavailable25nF(2K x 1K device) Serial per phase320pFunavailable50pF RGunavailable 10pF SW----10pF TG----100pF baseline

8. LSST Electronics Review – BNL, January 25-26 20128 FEB Voltages ASPIC power - +5V – local linear regulation from the PDS supplied +6-7V linear Vref +2.5V for ASPIC and ADCs - generated on BEB CABAC power – –Logic +5V (local linear regulation) –Bias +30V (OD [2 mA per CCD output], other biases at  A – from BEB DAC –Clock upper +12 (from DAC on BEB) –Clock lower 0-+1V (from DAC on BEB) OS current source fed from CABAC OD output

9. LSST Electronics Review – BNL, January 25-26 20129 RCC Voltages +5V analog, local linear regulator for ADCs and Diff Amps +5V analog, local linear regulator for DACs +35V and +15V inputs to BEB DACs to provide CABAC +5V digital for LVDS drivers, SPI devices Pass through of -70V for CCD substrate bias Digital supplies for FPGA on RCM – separate local regulation from +7V digital –+5V digital for FPGA –+3.3V digital for FPGA –+1.8V digital for FPGA

10. LSST Electronics Review – BNL, January 25-26 201210 Sequencing PDS is designed to allow software sequencing on power up or power down – e.g. –Turn on digital power –Configure FPGA –Test RCM digital behavior –Turn on some analog power –Further tests –Turn on all power –Verify operation –Full focal plane or raft by raft Emergency sequencing is not yet a requirement but we have not yet done a complete hazard analysis (this is somewhat vendor dependent) If any voltage sequence hazards are shown to exist we need to design a hardware protection scheme to prevent any dangerous relative potentials from happening (e.g. diodes)

11. LSST Electronics Review – BNL, January 25-26 201211 Protection Overvoltage and overcurrent built into PDS Raft Power Cards (hard coded limits) Very limited energy in each separate supply Fusing – makes sense on Raft Power Card for higher current supplies but not feasible for low current supplies (e.g. substrate bias) - NOTE that fuses are not allowed inside the cryostat (contamination worry)

12. End of Presentation