Advance Nano Device Lab. Fundamentals of Modern VLSI Devices 2 nd Edition Yuan Taur and Tak H.Ning 0 Ch4.2 Threshold Voltage.

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Presentation transcript:

Advance Nano Device Lab. Fundamentals of Modern VLSI Devices 2 nd Edition Yuan Taur and Tak H.Ning 0 Ch4.2 Threshold Voltage

Advance Nano Device Lab. Off-current and Standby Power 1

Advance Nano Device Lab. On-current and MOSFET Performance 2

Advance Nano Device Lab. 3

4

CMOS Design Considerations 5

Advance Nano Device Lab. CMOS Design Considerations 6

Advance Nano Device Lab. Trends of Power Supply Voltage and Threshold Voltage 7

Advance Nano Device Lab. 8 Trends of Power Supply Voltage and Threshold Voltage

Advance Nano Device Lab. Effect of Gate Work Function 9

Advance Nano Device Lab. Effect of Gate Work Function 10

Advance Nano Device Lab. Channel Profile Requirement and Trends 11

Advance Nano Device Lab. Integral Solution to Poisson’s Equation 12

Advance Nano Device Lab. A High-Low Step Profile 13

Advance Nano Device Lab. A High-Low Step Profile 14

Advance Nano Device Lab Threshold Voltage 15

Advance Nano Device Lab. A High-Low Step Profile 16

Advance Nano Device Lab. Generalization to a Gaussian Profile 17

Advance Nano Device Lab. Generalization to a Gaussian Profile 18

Advance Nano Device Lab. Retrograde (Low-High) Channel Profile 19

Advance Nano Device Lab. Extreme Retrograde Profile and Ground-Plance MOSFET 20

Advance Nano Device Lab. 21 Extreme Retrograde Profile and Ground-Plance MOSFET

Advance Nano Device Lab. 22 Extreme Retrograde Profile and Ground-Plance MOSFET

Advance Nano Device Lab Threshold Voltage 23

Advance Nano Device Lab. Counter-Doped Channel 24

Advance Nano Device Lab. Counter-Doped Channel 25

Advance Nano Device Lab. Laterally Nonuniform Channel Doping 26

Advance Nano Device Lab. 9.2 Ion Implantation and Substrate Nonuniformity 27

Advance Nano Device Lab. Future Transistors Complexi t y ≈ Evolutionary Revolutionary 2014 Short CourseGreg Yeric 11

Advance Nano Device Lab Short CourseGreg Yeric 73 Need to increase current densityas theFETs scale Ge PMOS III-V NMOS G e, InGaAs  vs. density of states Bandgap: BTBT, GIDL Oxides Quantum wells See Session 25

Advance Nano Device Lab Short CourseGreg Yeric Short CourseGreg Yeric Your Device IMEC. VLSI 2014 “7nm FinFETs” Technology14nm10nm7nm5nm VDDV Gate Pitchnm Metal Pitchnm Channel Lengthnm EOT + dark spacenm Fin pitchnm Max. fins per FET4444

Advance Nano Device Lab. No two identically designed transistors are alike anymore! Asenov et al, IEDM 2008  V T ~ 1/(WL) 1/2 100 The established simulation para digm Physical gate length 22nm atoms Failures shift from catastrophic to time-dependent variability This needs adaptations in circuit design to account for statistical spread in device parameters Physical gate length 9nm = 30x30x30 8 Challenges of 7nm CMOS Technology

Advance Nano Device Lab. Deeply-scaled Device operation becomes more and more affected by Individual defects In deeply-downscaled technologies, only a handful of random defects will be present in each device 72 Challenges of 7nm CMOS Technology N ot = cm -2  N T ~ 10 if device area = 10 x 100 nm 2 Numb er of charged defects will be increasing with operating time  time-dependent variability in addition to time-0 variability Courtesy of M. Bina, TUWien

Advance Nano Device Lab. Quantum Effect on Threshold Voltage 33

Advance Nano Device Lab. Quantum Effect on Threshold Voltage 34

Advance Nano Device Lab. Triangular Potential Approximation for the Subthreshold Region 35

Advance Nano Device Lab. Triangular Potential Approximation for the Subthreshold Region 36

Advance Nano Device Lab. Threshold-Voltage Shift Due to Quantum Effect 37

Advance Nano Device Lab. Quantum Effect on Inversion-Layer Depth 38

Advance Nano Device Lab. A Simple First-Order Model 39

Advance Nano Device Lab. Discrete Dopant Effects in a Retrograde-Doped Channel 40