Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 1 Raimund Ubar N.Mazurova, J.Smahtina, E.Orasson, J.Raik Tallinn Technical University Estonia MIXDES, Sczcecin, June 24, 2004 Hybrid Functional BIST in Microprogrammed Data-Paths of Digital Systems

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 2 Overview Motivation for BIST Overview of BIST methods Functional self-testing Hybrid Functional BIST Tradeoff calculation for HyFBIST Experimental results Future work

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 3 Built-In Self-Test in SoC System-on-Chip testing Test architecture components: Test pattern source & sink Test Access Mechanism Core test wrapper Solutions: Off-chip solution –need for external ATE Combined solution –mostly on-chip, ATE needed for control On-chip solution –BIST

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 4 Built-In Self-Test Components BIST components: –Test pattern generator (TPG) –Test response analyzer (TRA) TPG & TRA are usually implemented as –linear feedback shift registers (LFSR) or –cellular automata Two widespread schemes: –test-per-scan –test-per-clock

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 5 Built-In Self-Test Motivations for BIST: –Cost of ATE (Automated Test Equipment) –Increasing difficulties with TPG (Test Pattern Generation) –Growing volume of test pattern data –Test application time –Gap between tester and UUT (Unit Under Test) speeds Drawbacks of BIST: –Additional pins and silicon area needed –Decreased reliability due to increased silicon area –Performance impact due to additional circuitry –Additional design time and cost

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 6 Problems with BIST Problem: low fault coverage The main motivations of using random patterns are: - low generation cost - high initial efeciency 0 2 n -1 Possible patterns from LFSR: Pseudorandom test: Hard to test faults 0 2 n -1 Dream solution: find LFSR so that:

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 7 Problems with BIST Problem: low fault coverage Counter Decoder & LFSR Reset If Reset = 1 signal has probability 0,5 then counter will not work and 1 for AND gate may never be produced 1

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 8 Improving Fault Coverage Modifying ciruit under test (CUT) –Inserting test points [Rajski-96, Touba-96] –Redesigning CUT to improve testability [Pradhan-95, Touba-96,98] Drawback: additional logic added that degrades system performance Weighting pseudorandom sequence [Brglez-89, AlShaibi-96] –Additional logic to weight the probability of each bit in the test sequence Drawback: additional HW for storing of the weight sets + control logic Mixed mode approach –Using additional deterministic patterns [Koenemann-91] –Multipolynomial LFSR [Hellebrand-95] –Bit flipping (bit fixing) [Wunderlich-96, Touba-96] –Embedding deterministic test cubes into pseudorandom sequence Drawback: area overhead and performance degradation

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 9 Functional Self-Test Traditional BIST solutions use special hardware for pattern generation on chip, this may introduce area overhead and performance degradation New methods have been proposed which exploit specific functional units like arithmetic blocks or processor cores for on-chip test generation [Rajski/Tyszer-98, Wunderlich-98] It has been shown that adders can be used as test generators for pseudorandom and deterministic patterns Today, there is no general method how to use arbitrary functional units for built-in test generation

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 10 Hybrid Functional BIST In this paper we propose a mixed-mode or hybrid functional BIST (HyFBIST) for using in microprogrammed data-paths in digital systems The idea of the HyFBIST consists in using for test purposes the mixture of functional patterns –produced by the microprogram (no additional HW is needed), and –additional stored deterministic test patterns to improve the total fault coverage Tradeoff is found between –the testing time and –the cost of additional area

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 11 Functional Self-Test Data compression in FBIST: Register block Control ALU Signature analyser Functional test Data K N=120 cycles K*N Fault simulator Fault coverage Test patterns are produced on- line during the working mode of the system B D =64 B m =105 Data compression: NB m / B D

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 12 Functional Self-Test Fault coverage of FBIST compared to functional test:

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 13 Hybrid Functional BIST Implementation phase Functional test Deterministic test

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 14 BIST Embedding Example M1M2 M3 M5 LFSR1 M4 MISR1 BILBO M6 MUX CSTP LFSR2 MISR2 MUX LFSR, CSTP  M2  MISR1 M2  M5  MISR2 (Functional BIST) CSTP  M3  CSTP LFSR2  M4  BILBO Concurrent testing:

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 15 Tradeoff Between F/D Test Parts  C FB_T +  C FB_M C D_Const Cost C Total = C FB_Total +C D_Total C FB_Const Length of FBIST Opt. cost Opt. length  C D_T +  C D_M C TOTAL – total cost of the hybrid FBIST C FB_Total - functional test C D_Total - deterministic test

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 16 Deterministic Test Length Estimation Fault coverage: Deterministic test Estimation Functional test

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 17 Iterative optimization of HyFBIST  C FB_T +  C FB_M C D_Const Cost C Total = C FB_Total +C D_Total C FB_Const Length of FBIST Opt. cost Opt. length  C D_T +  C D_M Predicted total cost ’ 1’ 4 5 Predicted cost of deterministic test 2’ – Observation 2 – Calculation 3 – Observation 4 – Calculation 5 – Observation 6 – Observation 7 – Calculation 8 – Observation 5 – Decision

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 18 Experimental Results Selected functional tests as single procedures: A single division procedure for a single pair of data (A,B) is not able to produce high fault coverage Series of experiments was carried out to merge several division procedures into a single functional test

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 19 Experimental Results The progress of parameters at the increasing length k of the functional test is shown for the best combination of functional and deterministic test parts The gain compared to pure deterministic test – 2,8 times

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 20 Experimental Results A selection of 6 experiments is presented K is the optimal number of runs of the microprogram (optimal length of the functional test part)

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 21 Conclusions We introduced a new approach to functional BIST based on three ideas: –to use in microprogrammed digital systems cyclically online produced data as test patterns, –to combine this type of test with additional deterministic test patterns to achieve 100% fault coverage, and –to find an optimal combination of both test parts. Experiments showed the feasibility and efficiency of this approach. The data compression in FBIST was 197 The gain in test cost for HyFBIST compared to pure deterministic test was 2,8 times

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 22 Future work The global problem of finding hybrid FBIST with minimum cost is more complex than only finding the best functional part, and then optimizing the HyFBIST The experiments showed that the best functional test part with highest fault coverage 89,1% does not quarantee the best hybrid FBIST Optimization of HyFBIST in a global sense will be the future research of authors