Orange Coast College Business Division Computer Science Department CS 116- Computer Architecture Arithmetic: Part II

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 2 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Universal ALU All the previous logic is referred to Universal ALU Symbolic representation: – (Sometimes used to represent adders as well) 32 Operation Result a b ALU Zero Flag C out from MSB C in to LSB Overflow Flag

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 3 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Key Observations We can build an ALU to support the MIPS instruction set – Key idea: Use multiplexor to select the output we want – We can efficiently perform subtraction using two’s complement – We can replicate a 1-bit ALU to produce a 32-bit ALU – For ripple-carry adders, the C out of one stage is used as C in to the following stage

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 4 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Hardware Observations All of the gates are always working – Not disabled Speed of gate depends on number of inputs – Fan-in Speed of circuit depends on critical path – Propagation delays of gates in series – Critical path or the “Deepest level of logic” Minimum number of gates before the circuit can be evaluated Determines the minimum length of time in which the project can be completed

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 5 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) The Payoff Clever changes to organization can improve performance – Similar to using better algorithms in software

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 6 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Design Options for Adders Two extremes: – Ripple carry C i depends on the operation in the adjacent 1-bit adder MSB of the sum must wait for the sequential evaluation of all 32, 1-bit adders Too slow to be used in time-critical hardware – Sum-of-products Can evaluate everything at once Any equation can be represented using 2-level logic Very complicated for 32-bits

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 7 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Design Options for Adders Compromise! – Carry look-ahead (CLA) Carries are faster All logic begins evaluation at the begin of the clock cycle Takes shortcut by going through fewer gates to send the carry-in signal

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 8 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Ripple Carry Adder To evaluate c 4 need c 3, that needs c 2,etc... c 1 = b 0 c 0 + a 0 c 0 + a 0 b 0 c 2 = b 1 c 1 + a 1 c 1 + a 1 b 1 =... c 3 = b 2 c 2 + a 2 c 2 + a 2 b 2 =... c 4 = b 3 c 3 + a 3 c 3 + a 3 b 3 =... Can you see the ripple? – Each result needs values from previous calculation

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 9 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Ripple Carry Adders- Transformation How could you get rid of the ripple? – What about substituting for c 1 into c 2 ? c 1 = b 0 c 0 + a 0 c 0 + a 0 b 0 c 2 = b 1 (b 0 c 0 + a 0 c 0 + a 0 b 0 ) + a 1 (b 0 c 0 + a 0 c 0 + a 0 b 0 ) + a 1 b 1 =... – The equation expands exponentially with the number of bits Expensive HW

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 10 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Carry-Lookahead Adder An approach in-between our two extremes Motivation: – If don't know what the carry-in is, what to do? c i+1 = b i c i + a i c i + a i b i = a i b i + (a i + b i )c i c 2 = a 1 b 1 + (a 1 + b 1 )c 1 = a 1 b 1 + (a 1 +b 1 )+((a 0 b 0 +(a 0 +b 0 )c 0 ) – When would we always generate a carry? Let g i = a i b i (g for generate) – When would we propagate the carry? Let p i = a i + b i (p for propagate)

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 11 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Let's generalize the equations General format: c i+1 = g i + p i c i – If g i = 1 => c i+1 = 1 (adder generates carry out independent of ci ) – If g i = 0 & p i = 1 => c i+1 = c i (adder propagates carry in to cout )

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 12 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Carry Lookahead Adders Two definitions are the key to CLA logic: – For a certain inputs (a i =1& b i =1), at stage i, a carry is generated independent of previous values ( a 0..a i-1, b 0..b i-1, c 0 ) g i = a i * b i – For certain inputs and a carry input ( c i =1 and either a i =1 or b i =1), at stage i, a carry is generated independent of previous values ( a 0..a i-1, b 0..b i-1, c 0 ) p i = a i + b i

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 13 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Carry Lookahead Adders Generates a carry if both its addend bits = 1 Propagates carry if at least one addend bit = 1 c 1 = g 0 +p 0.c 0 c 2 = g 1 +p 1.g 0 +p 1.p 0.c 0 c 3 = g 2 +p 2.g 1 +p 2.p 1.g 0 +p 2.p 1.p 0.c 0 c 4 = g 3 + p 3.g 2 + p 3.p 2.g 1 + p 3.p 2.p 1.g 0 + p 3.p 2.p 1.p 0.c 0 Each equation corresponds to a circuit with just 3-levels of delay – 1-level for generate & propagate – 2-levels for sum-of-products

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 14 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Carry Lookahead Adders Each equation corresponds to a circuit with just 3-levels of delay – 1-level for generate & propagate P0 = p3. p2. p1. p0 P1 = p7. p6. p5. p4 P2 = p11. p10. p9. p8 P3 = p15. p14. p13. p12 – 2-levels for sum-of-products G0= g3+(p3.g2)+(p3.p2.g1)+(p3.p2.p1.g0) G1= G0+(P0.c0) G2= G1+(P1.G0)+(P1.P0.c0) G3= G2+(P2.G1)+(P2.P1.G0)+(P2.P1.P0.co) G4=G3+(P3.G2)+(P3.P2.G1)+(P3.P2.P1.G0)+(P3.P2.P1.P0.c0)

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 15 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Carry Lookahead Adders- Example Example: – Determine gi, pi, Pi & Gi values for the following 16-bit numbers: a: b: Solution: gi=ai*bi: pi=ai+bi:

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 16 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Carry Lookahead Example For the propagate P3 = p15*P14*p13*p12 = 1*1*1*1 = 1 P2 = p11*P10*p9*p8 = 1*1*1*1 = 1 P1 = p7*p6*p5*p5 = 1*1*1*1 = 1 P0 = p3*p2*p1*p0 = 1*0*1*1= 0 For the generate G0 = g3+(p3*g2)+(p3*p2*g1)+(p3*p2*p1*g0) = 0+(1*0)+(1*0*1)+(1*0**11) = = 0 G1 = g7+(p7*g6)+(p7*p6*g5)+(p7*p6*p5*g4) = 0+(1*0)+(1*1*1)+(1*1*1*0) = 1 G2 = g11+(p11*g10)+(p11*p10*g9)+(p11*p10*p9*g8) = 0+(1*0)+(1*1*0)+(1*1*1*0) = 0 G3 = g15+(p15*g14)+(p15*p14*g13)+(p15*p14*p13*g12) = 0+(1*0)+(1*1*0)+(1*1*1*0) = 0 For the carry from the add C4 = G3+(P3*G2)+(P3*P2*G1)+(P3*P2*P1*G0)+(P3*P2*P1*P0*c0) = 0+(1*0)+(1*1*1)+(1*1*10)+(1*1*1*0*0) = 1

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 17 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Bigger CLAs To build bigger adders: – Can’t build a 16 bit adder this way – Could use Ripple carry of 4-bit CLA adders – Even Better: use the CLA principle again! – Notice: The carries come from the CLA unit, not from the 4-bit ALU’s

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 18 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Multiplication 0010 (multiplicand) x0011 (multiplier) (product) Process – Take the digits of the multiplier from right to left – Multiply each digit of the multiplier by the multiplicand – Shift intermediate products, one digit to the left

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 19 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Multiplication Assumptions – n-bit in the multiplicand – m-bits in the multiplier Product will contain (n+m)-bits Product needs more space Overflow during multiplication can occur

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 20 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Multiplication More complicated than addition – Successive shifting and addition – More time If multiplier = 1 – Place a copy of the multiplicand in proper place If multiplier = 0 – Place 0 in proper place

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 21 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Unsigned Multiplication: Version 1 Hardware Implementation 64 - b it A L U Con tr o l t es t Product Write Multiplicand Shift left Multiplier Shift Right 64 b it s 64 b it s 32 b it s

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 22 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Unsigned Multiplication – Version1: HW Characteristics – Uses 3-Registers: Multiplicand register (64-bits): – Multiplicand starts in right half – Needs shift left 1 BIT EACH STEP Multiplier register (32-bits): – Needs shift right 1 BIT EACH STEP Product (64-bits): – Initially 0 – Needs Write operation – Adder 64-bits wide – Control test unit decides when to shift & when to write new values into product register

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 23 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Unsigned Multiplication-Version 1 D o n e Start Multiplier 0 = 1 Yes: 32 repetitions Multiplier 0 = 0 1 Test Multiplier 0 32 nd Repetition? 1a. Add multiplicand to product and place the result in Product register 2. Shift the Multiplicand register left 1 bit 3. Shift the Multiplier register right 1 bit

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 24 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Unsigned Multiplication-Version 1 Algorithm characteristics: – Three basic steps: Test LSB of multiplier Add Multiplicand to product Shift Multiplicand one bit to the left & Multiplier to the right Disadvantage: – Too long – For 2 32-bit numbers: If each step needs 1 cycle => ~ 100 cycles needed to finish the multiplication

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 25 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Unsigned Multiply- Example : 0  no operation 2: Shift Mcand left 3:Shift Mplr right : 0  no operation 2: Shift Mcand left 3:Shift Mplr right a:1  Prod=Pd+Mcnd 2: Shift Mcand left 3:Shift Mplr right a:1  Prod=Pd+Mcnd 2: Shift Mcand left 3:Shift Mplr right Initial values0 ProductMultiplicandMultiplierStepIteration Example: Multiply 2 10 x 3 10 = x

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 26 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Unsigned Multiply Observations: – Half of the bits of the multiplicands are always 0 – A full 64-bit ALU is wasteful & slow Half of adder bits are adding 0’s to intermediate sum – What happens if we shift product to the right instead of shifting multiplicand to the left?

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 27 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Unsigned Multiply- Revision 2 Multiplier Shift right 32 bits Write Shift right Multiplicand 32-bit ALU 64 bits Product Control test

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 28 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Unsigned Multiplication- Version 2 HW Characteristics: – Uses 3-Registers: Multiplicand register (32-bits): – Multiplicand is fixed relative to the product Multiplier register (32-bits): – Needs shift right Product (64-bits): – Needs shift right and Write operations – Adder (ALU) only 32-bits wide

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 29 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Unsigned Multiplication- Version 2 D o n e Start Multiplier 0 = 1 Yes: 32 repetitions Multiplier 0 = 0 1 Test Multiplier 0 32 nd Repetition? 1a. Add multiplicand to left half of product and place the result in left half of Product register 2. Shift the Product register right 1 bit 3. Shift the Multiplier register right 1 bit

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 30 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Unsigned Multiple 2- Example : 0  no operation 2: Shift Prod right 3:Shift Mplr right : 0  no operation 2: Shift Prod right 3:Shift Mplr right a:1  Prod=Pd+Mcnd 2: Shift Prod right 3:Shift Mplr right a:1  Prod=Pd+Mcnd 2: Shift Prod right 3:Shift Mplr right Initial values0 ProductMultiplicandMultiplierStepIteration Example: Multiply 2 10 x 3 10 = x

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 31 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Getting closer The product register has unused space – Exactly the size of multiplier – As wasted space is reduced by 1 bit, so is multiplier The two right shifts – Therefore, can use bottom half of product register for multiplier

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 32 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Control test 32 bits Write 64 bits Produ ct Multiplicand 32-bit ALU Shift right

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 33 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Unsigned Multiplier Final HW characteristics: – Combine rightmost half of product with multiplier The LSB of product register is the bit to be tested No need for a separate multiplier register – Only 2-Registers are needed: Multiplicand register (32-bits): – needs shift left Product (64-bits): – Needs shift right and Write operations – Start with the multiplier in the rightmost half of the product register and 0’s in the upper half

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 34 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Unsigned Multiply Final- Algorithm D o n e Start Multiplier 0 = 1 Yes: 32 repetitions Multiplier 0 = 0 1 Test Multiplier 0 32 nd Repetition? 1a. Add multiplicand to left half of product and place the result in left half of Product register 2. Shift the Product register right 1 bit

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 35 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Unsigned Multiply Final- Example : 0  no operation 2: Shift Prod right : 0  no operation 2: Shift Prod right a:1  Prd=Prd+Mcnd 2: Shift Prod right a:1  Prd=Prd+Mcnd 2: Shift Prod right Initial values0 ProductMultiplicandStepIteration Example: Multiply 2 10 x 3 10 = x

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 36 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Signed Multiplication First convert the multiplier & multiplicand to +ve numbers Remember the original sign Negate the product if the signs disagree Can also use Booth's Algorithm – Book contains more information

OCC - CS/CIS CS116-Ch00-Orientation Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 37 OCC-CS 116 Fall Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Multiply in MIPS MIPS provides a separate pair of 32-bit register to contain 64-bit products called – Hi & Lo Two instructions – Multiply: mult – Multiply unsigned: multu Fetch product instructions – Move from Lo : mflo – Move from Hi : mfhi MIPS multiply instructions ignore overflow – It is up to the SW to check for overflow