1. COMP541 Arithmetic Circuits
Montek Singh
Oct 21, 2015

2. Today’s Topics Adder circuits Subtraction Overflow
ripple-carry adder (revisited)
more advanced: carry-lookahead adder
Subtraction
by adding the negative
Overflow

3. Iterative Circuit
Like a hierarchy, except functional blocks per bit

4. Adders Great example of this type of design
Design 1-bit circuit, then expand
Let’s look at
Half adder – 2-bit adder, no carry in
Inputs are bits to be added
Outputs: result and possible carry
Full adder – includes carry in, really a 3-bit adder
We have already studied adder in Lab 3/Comp411
here we look at it from a different angle
modify it to be faster

5. Half Adder
Produces carry out
does not handle carry in

6. Full Adder Three inputs Two outputs third is carry in
sum and carry out

7. Two Half Adders (and an OR)

8. Ripple-Carry Adder Straightforward – connect full adders
32-bit ripple-carry adder
Straightforward – connect full adders
Carry-out to carry-in chain
Cin in case this is part of larger chain, or just ‘0’

9. Lab 3: Hierarchical 4-Bit Adder
We used hierarchy in Lab 3
Design full adder
Used 4 of them to make a 4-bit adder
Used two 4-bit adders to make an 8-bit adder …

10. Specifying Addition in Behavioral Verilog
// 4-bit Adder: Behavioral Verilog
module adder_4_behav(A, B, C0, S, C4);
input wire[3:0] A, B;
input wire C0;
output logic[3:0] S;
output logic C4;
assign {C4, S} = A + B + C0;
endmodule
Addition (unsigned)
Concatenation operation

11. What’s the problem with this design?
Delay
Approx how much?
Imagine a 64-bit adder
Look at carry chain

12. Delays (after assigning delays to gates)
Delays are generally higher for more significant bits

13. Multibit Adders Several types of carry propagate adders (CPAs) are:
Ripple-carry adders (slow)
Carry-lookahead adders (fast)
Prefix adders (faster)
Carry-lookahead and prefix adders are faster for large adders but require more hardware.
Adder symbol (right)

14. Carry Lookahead Adder Note that add itself just 2 level
sum is produced with a delay of only two XOR gates
carry takes three gates, though
Idea is to separate carry from adder function
then make carry faster
actually, we will make carry have a 2-gate delay total, for all the bits of the adder!
these two gates might be huge though

15. Four-bit Ripple Carry Reference Adder function separated from carry
Notice adder has A, B, C in
and S out, as well as G,P out.

16. Propagate The P signal is called propagate
P = A  B
Means to propagate incoming carry

17. Generate The G is generate So it’s ORed with incoming carry
G = AB, so new carry created
So it’s ORed with incoming carry

18. Said Differently
If A  B and there’s incoming carry, carry will be propagated
And S will be 0, of course
If AB, then will create carry
Incoming will determine whether S is 0 or 1

19. Ripple Carry Delay: 8 Gates
Key observation:
G and P are produced by each adder stage
without needing carry from the right!
need only 2 gate delays for all G’s and P’s to be generated!
critical path is the carry logic at the bottom
the G’s and P’s are “off the critical path”

20. Turn Into Two Gate Delays
Refactor the logic
changed from deep (in delay) to wide
for each stage, gather and squish together all the logic to the right

21. C1 Just Like Ripple Carry

22. C2 Circuit Two Levels G from before and P to pass on
This checks two propagates and a carry in

23. C3 Circuit Two Levels Generate from level 0 and two propagates
G from before and P to pass on
This checks three propagates and a carry in

24. What happens as scaled up?
Can I realistically make 64-bit adder like this?
Have to AND 63 propagates and Cin!
Compromise
Hierarchical design
More levels of gates
use a tree of AND’s
delay grows only logarithmically

25. Making 4-Bit Adder Module
Create propagate and generate signals for whole module

26. Group Propagate
Make propagate of whole 4-bit block
P0-3 = P3P2P1P0

27. Group Generate
Indicates carry generated within this block

28. Hierarchical Carry Left lookahead block is exercise for you
4-bit adder A B S G P
Cin C0
Look Ahead C8 C4
Left lookahead block is exercise for you

29. Practical Matters FPGAs like ours have limited inputs per gate
Instead they have special circuits to make adders
So don’t expect to see same results as theory would suggest

30. Other Adder Circuits What if hierarchical lookahead too slow
Other styles exist
Prefix adder (explained in text) had a tree to computer generate and propagate
Pipelined arithmetic units – multicycle but enable faster clock speed
These are for self-study

31. Adder-Subtractor
Need only adder and complementer for input to subtract
Need selective complementer to make negative output back from 2’s complement

32. Design of Adder/Subtractor
S low for add,
high for subtract
Inverts each bit of B if S is 1
Adds 1 to make 2’s complement
Output is 2’s complement if B > A

33. Overflow Two cases of overflow for addition of signed numbers
Two large positive numbers overflow into sign bit
Not enough room for result
Two large negative numbers added
Same – not enough bits
Carry out by itself doesn’t indicate overflow

34. Overflow Examples 4-bit signed numbers:
Sometimes a leftmost carry is generated without overflow:
-7 + 7
5 + (-3)
Sometimes a leftmost carry is not generated, but overflow occurs:
4 + 4

35. Overflow Detection Basic condition:
if two +ve numbers are added and sum is –ve
if two -ve numbers are added and sum is +ve
Can be simplified to the following check:
either Cn-1 or Cn is high, but not both

36. Summary Today Next class: adders and subtractors overflow
full processor datapath