2. 1 (Based on text: David A. Patterson & John L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, 3 rd Ed., Morgan Kaufmann, 2007) Computer Arithmetic

3. 2 COURSE CONTENTS Introduction Instructions è Computer Arithmetic Performance Processor: Datapath Processor: Control Pipelining Techniques Memory Input/Output Devices

4. 3 COMPUTER ARITHMETIC Arithmetic Logic Unit (ALU) Fast Adder

5. 4 Foundation Knowledge Decimal, Binary, Octal, & Hexadecimal Numbers Signed & Unsigned Numbers 2’s Complement Representation 2’s Complement Negation, Addition, & Subtraction Overflow Sign Extension ASCII vs Binary Boolean Algebra Logic Design Assembly Language

6. 5 Numbers Bits are just bits (no inherent meaning) Conventions define relationship between bits and numbers Binary numbers (base 2) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001... decimal: 0... 2 n – 1 Of course it gets more complicated: Numbers are finite (overflow) Fractions and real numbers Negative numbers E.g., no MIPS subi instruction; addi can add a negative number How do we represent negative numbers? I.e., which bit patterns will represent which numbers?

7. 6 Possible Representations Three representations Sign Magnitude: One's Complement Two's Complement 000 = +0000 = +0000 = +0 001 = +1001 = +1001 = +1 010 = +2010 = +2010 = +2 011 = +3011 = +3011 = +3 100 = -0100 = -3100 = -4 101 = -1101 = -2101 = -3 110 = -2110 = -1110 = -2 111 = -3111 = -0111 = -1 Issues: balance, number of zeros, ease of operations Which one is best? Why?

8. 7 MIPS 32 bit signed numbers: 0000 0000 0000 0000 0000 0000 0000 0000 two = 0 ten 0000 0000 0000 0000 0000 0000 0000 0001 two = + 1 ten 0000 0000 0000 0000 0000 0000 0000 0010 two = + 2 ten... 0111 1111 1111 1111 1111 1111 1111 1110 two = + 2,147,483,646 ten 0111 1111 1111 1111 1111 1111 1111 1111 two = + 2,147,483,647 ten 1000 0000 0000 0000 0000 0000 0000 0000 two = – 2,147,483,648 ten 1000 0000 0000 0000 0000 0000 0000 0001 two = – 2,147,483,647 ten 1000 0000 0000 0000 0000 0000 0000 0010 two = – 2,147,483,646 ten... 1111 1111 1111 1111 1111 1111 1111 1101 two = – 3 ten 1111 1111 1111 1111 1111 1111 1111 1110 two = – 2 ten 1111 1111 1111 1111 1111 1111 1111 1111 two = – 1 ten maxint: + 2,147,483,647 ten minint: – 2,147,483,648 ten

9. 8 Two’s Complement Operations Negating a two’s complement number: invert all bits and add 1 Remember: “negate” and “invert” are quite different! Converting n bit numbers into numbers with more than n bits: MIPS 16 bit immediate gets converted to 32 bits for arithmetic Copy the most significant bit (the sign bit) into the other bits 0010 -> 0000 0010 1010 -> 1111 1010 “sign extension” (lbu vs. lb)

10. 9 Additional MIPS Instructions Character transfer lbu $s1, 100($s2)# $s1  memory [$s2+100] (load byte unsigned) sb $s1, 100($s2)# memory [$s2+100]  $s1 (store byte) Conditions sltu $s2, $s3, $s4# if ($s3) < ($s4) then $s2  1; # else $s2  0 (set on less than, unsigned numbers) # Note that slt works on 2’ complement numbers Arithmetic on unsigned numbers addu $s1, $s2, $s3# $s1  $s2 + $s3 (no overflow detection) subu $s1, $s2, $s3# $s1  $s2 - $s3 (no overflow detection) addiu $s1, $s2, 100 # $s1  $s2 + 100 (no overflow detection) MIPS detects overflow with an exception (interrupt), which is an unscheduled procedure call. MIPS includes a register, called exception program counter (EPC) to contain the address of the instruction that caused the exception mfc0 $s1, $epc # $s1  $epc (move from special registers)

11. 10 Shift operations sll $t2, $s0, 8 # $t2  $s0 >10 (shift right by constant) Fill the emptied bits with 0’s Logical operations and $s1, $s2, $s3 # $s1  $s2 and $s3 (bit-by-bit and) or $s1, $s2, $s3 # $s1  $s2 or $s3 (bit-by-bit or) andi $s1, $s2, 100 # $s1  $s2 and 100 ori $s1, $s2, 100 # $s1  $s2 or 100 Op=0 rs=0 rt=16 rd=10 shamt=8 funct=0 sll $t2, $s0, 8 Additional MIPS Instructions

12. 11 ALU: Arithmetic Logic Unit Performs arithmetic (e.g. add) & logical operations (e.g. and) in CPU ControlFunctResult 000andA and B 001orA or B 010addA + B 110subA - B 111slt1 if A<B A B ALU operation Zero Result Overflow 32 Carryout 32

13. 12 ALU Building Blocks 1-bit adder Gates, multiplexor c out = a b + a c in + b c in sum = a  b  c in Note: Cin is carryin, cout is carryout Sum CarryIn C arryOut a b

14. 13 A Simple ALU b 0 2 Result Operation a 1 CarryIn CarryOut A 1-bit ALU that performs AND, OR, and addition (shown below) Building a 32-bit ALU (shown right)

15. 14 Two's complement approach: just negate b and add. How do we negate? By selecting Binvert = 1, and setting CarryIn =1 in the least significant bit of ALU, we get 2’s complement subtraction a - b ALU: Subtraction 0 2 Result Operation a 1 CarryIn CarryOut 0 1 Binvert b

16. 15 To support set-on-less-than instruction (slt) slt is an arithmetic instruction produces a 1 if rs < rt and 0 otherwise use subtraction: (a-b) < 0 implies a < b use a Set & a Less signal to indicate result To support test for equality (beq) use subtraction: (a-b) = 0 implies a = b ALU: Additional Operations

17. 16 ALU: Additional Operations 0 3 Result Operation a 1 CarryIn CarryOut 0 1 Binvert b 2 Less A 1-bit ALU that performs AND, OR, add, subtract: Less is used for slt instruction (see 32-bit ALU next slide) The ALU for the most significant bit: Set is used for slt instruction, it is connected to Less of lsb (see 32-bit ALU next slide) Overflow detection needed on msb 0 3 Result Operation a 1 CarryIn 0 1 Binvert b 2 Less Set(sign) Overflow detection Overflow

18. 17 A 32-bit ALU that performs AND, OR, add, & subtract For subtract, set Binvert = 1 and CarryIn =1 (for add or logical operations, both set to 0) Can combine Binvert & CarryIn to Bnegate Set and Less, together with subtraction, can be used for slt Set(sign) a31 0 ALU0 Result0 CarryIn a0 Result1 a1 0 Result2 a2 0 Operation b31 b0 b1 b2 Result31 Overf l ow Binvert CarryI n Less CarryIn CarryOu t ALU1 Less CarryIn CarryOut ALU2 Less CarryIn CarryOut ALU31 Less CarryIn CarryOut A 32-bit ALU

19. 18 A Final 32-bit ALU Add a zero detector to test for zero results or equality (e.g. in beq instruction) Control lines (Operation) (3-bit): 000 = and 001 = or 010 = add 110 = subtract 111 = slt bit1 & bit0 to multiplexors in ALU bit2 to Bnegate Note: zero is a 1 when the result is zero! Set a31 0 Result0 a0 Result1 a1 0 Result2 a2 0 Operation b31 b0 b1 b2 Result31 Overflow Bnegate Zero ALU0 Less CarryIn CarryOut ALU1 Less CarryIn CarryOut ALU2 Less CarryIn CarryOut ALU31 Less CarryIn 3 bits (Sign) CarryOut 1 bit 2 bits

20. 19 ALU Design: Summary Select building blocks: adders, gates Use multiplexors to select the output we want Perform subtraction using two’s complement Replicate a 1-bit ALU to produce a 32-bit ALU --> regularity Need circuit to detect conditions e.g. zero result, overflow, sign, carry out Shift instructions: Done outside the ALU by barrel shifter, which can shift from 1 to 31 bits in no more time than it takes to add two 32 bit numbers using carry lookahead adders Important points about hardware all of the gates are always working the speed of a gate is affected by the number of inputs to the gate the speed of a circuit is affected by the number of gates in series (on the “critical path” or the “deepest level of logic”) Our primary focus: comprehension, however, Clever changes to organization can improve performance (similar to using better algorithms in software)

21. 20 Ripple carry adder is just too slow: The sequential chain reaction is too slow for time-critical hardware Is a 32-bit ALU as fast as a 1-bit ALU? Is there more than one way to do addition? two extremes: ripple carry and sum-of-products Can you see the ripple? How could you get rid of it? Carry Lookahead Adder ++++

22. 21 Carry lookahead adder (CLA): an approach in-between our two extremes Motivation: If we didn't know the value of carry-in, what could we do? When would we always generate a carry? g i = a i b i When would we propagate the carry? p i = a i + b i Did we get rid of the ripple? c i+1 = g i + p i c i c 1 = g 0 + p 0 c 0 c 2 = g 1 + p 1 c 1 = g 1 + p 1 g 0 + p 1 p 0 c 0 c 3 = g 2 + p 2 c 2 = g 2 + p 2 g 1 + p 2 p 1 g 0 + p 2 p 1 p 0 c 0 c 4 = g 3 + p 3 c 3 = g 3 + p 3 g 2 + p 3 p 2 g 1 + p 3 p 2 p 1 g 0 + p 3 p 2 p 1 p 0 c 0 è Carry lookahead! Carry Lookahead Adder

23. 22 Can’t build a 16 bit adder using the g i & p i CLA method --> too big Could use ripple carry of 4-bit CLA adders Better: use the CLA principle again! (see left figure) Building Bigger Adders CarryIn Result0--3 ALU0 CarryIn Result4--7 ALU1 CarryIn Result8--11 ALU2 CarryIn CarryOut Result12--15 ALU3 CarryIn C1 C2 C3 C4 P0 G0 P1 G1 P2 G2 P3 G3 pi gi pi + 1 gi + 1 ci + 1 ci + 2 ci + 3 ci + 4 pi + 2 gi + 2 pi + 3 gi + 3 a0 b0 a1 b1 a2 b2 a3 b3 a4 b4 a5 b5 a6 b6 a7 b7 a8 b8 a9 b9 a10 b10 a11 b11 a12 b12 a13 b13 a14 b14 a15 b15 Carry-lookahead unit

24. 23 Summary Review number system Additional MIPS instructions The design of an ALU Carry lookahead adder