1. 240-334 By Wannarat 240-334 Computer System Design Lecture 3 Wannarat Suntiamorntut

2. 240-334 By Wannarat Arithmetic for Computer Implementing the Architecture

3. 240-334 By Wannarat The numbers Binary number (base 2) numbers are finite (overflow) fraction and real number negative number e.g., No MIPS subi instruction, addi can add a negative number

4. 240-334 By Wannarat Possible Representations Sign MagnitudeOne’s complementTwo’s complement 000 = +0 000 = +0 000 = +0 001 = +1 001 = +1 001 = +1 010 = +2 010 = +2 010 = +2 011 = +3 011 = +3 011 = +3 100 = -0 100 = -3 100 = -4 101 = -1 101 = -2 101 = -3 110 = -2 110 = -1 110 = -2 111 = -3 111 = -0 111 = -1 Negative and Invert are different!

5. 240-334 By Wannarat Addition & Subtraction 7 - 6 {0111 - 0110} = 0001 two’s complement 0111 + 1010 = 0001 Overflow n-bit does not yield an n-bit number 0111 + 0001 1000

6. 240-334 By Wannarat Detecting overflow No overflow when add positive&negative No overflow when signs are the same for subtraction Overflow occur when : - add two positives yield a negative - add two negative gives a positive - subtract negative from positive and get negative - subtract positive from negative get a positive

7. 240-334 By Wannarat Effect of Overflow Exception occur (Interrupt) - control jumps to predefined address for exception - Interrupted address is saved Don’t always to detect overflow - New MIPS instructions: addu, addiu...

8. 240-334 By Wannarat ALU Build ALU support andi, ori instructions

9. 240-334 By Wannarat Multiplexor Select one of the inputs to be output, base on control input

10. 240-334 By Wannarat ALU for Addition instruction Cout = ab + bc in + ac in Sum = a xor b xor c in

11. 240-334 By Wannarat ALU for Subtraction instruction Two’s complement approach : just negative b and ADD

12. 240-334 By Wannarat Supporting slt

13. 240-334 By Wannarat

14. MIPS Arithmetic Instruction format

15. 240-334 By Wannarat Conclusion ALU in MIPS Use multiplexor to select output we want efficiently perform subtraction using two’s complement replicate 1-bit ALU to 32-bit ALU

16. 240-334 By Wannarat Computation Problem :fast adder 32-bit ALU faster than 1-bit ALU? Carry-lookahead adder g = ab,p = a + b c1 = g0 + p0c0 c2 = g1 + p1c1c2 c3 = g2 + p2c2c3...

17. 240-334 By Wannarat

18. Part II : Lecture III

19. 240-334 By Wannarat Multiplication 0010(multiplicand) x1011 (multiplier) ????

20. 240-334 By Wannarat Unsign Combinational Multiplier

21. 240-334 By Wannarat Multiplication : First Version (Unsign)

22. 240-334 By Wannarat Multiplication : First Version (contd.)

23. 240-334 By Wannarat Analyze First Version 1 clock per cycle 50 % of bit in multiplicand always = 0 => 64-bit adder is wasted 0’s inserted in left of multiplicand as shifted => lead significant bits of product never changed once formed

24. 240-334 By Wannarat Multiplication : Second Version

25. 240-334 By Wannarat Multiplication : Second Version (Contd.)

26. 240-334 By Wannarat Analyze Second Version Product register wasted space that exactly matches size of multiplier Combine Multiplier register and Product register

27. 240-334 By Wannarat Multiplication : Third Version

28. 240-334 By Wannarat Multiplication : Third Version (Contd.)

29. 240-334 By Wannarat Analyze Third Version 2 steps per bit because multiplier & product combined MIPS registers Hi, Lo are left and right half of product

30. 240-334 By Wannarat Booth’s Algorithm

31. 240-334 By Wannarat Example : 2 x 7

32. 240-334 By Wannarat Example : 2 x -3

33. 240-334 By Wannarat Shifter : 2 kinds

34. 240-334 By Wannarat Part III : Lecture III

35. 240-334 By Wannarat Divide

36. 240-334 By Wannarat Divide : First Version

37. 240-334 By Wannarat Divide : First Version (Contd.)

38. 240-334 By Wannarat Analyze First Version 50%bits in divisor always 0 =>1/2 of 64-bit adder is wasted => 1/2 divisor is wasted 1 step cannot produce a 1 in quotient bit => Switch order to shift first

39. 240-334 By Wannarat Divide : Second Version

40. 240-334 By Wannarat Divide : Second Version (Contd.)

41. 240-334 By Wannarat Analyze Second Version Eliminate Quotient register by combining with Remainder as shifted left

42. 240-334 By Wannarat Divide : Third Version

43. 240-334 By Wannarat Divide : Third Version (Contd.)

44. 240-334 By Wannarat Analyze Third Version Do Analyze by yourself

45. 240-334 By Wannarat Floating Point : IEEE754

46. 240-334 By Wannarat Floating-point Representation -0.75 = -3/4 = -3/2 2 = -11/ 2 2 = -0.11= -1.1x 2 -1 = (-1) s x (1 + signifiand) x 2 (exponent-127) = (-1) x (1+.1000 0000) x 2 (126-127) 1 01111110 1000 0000 0000 0000 0000 000 S E M 1-bit 8-bit 23-bit

47. 240-334 By Wannarat Floating-point Addition 9.999 x 10 1 + 1.610x10 -1 Step1 : Change exponent as : 1.610 x 10 -1 = 0.016 x 10 1 Step2 : Add significands 9.999 (10) + 0.016 (10) 10.015 (10) Sum = 10.015 x 10 1

48. 240-334 By Wannarat Floating-point Addition 9.999 x 10 1 + 1.610x10 -1 Step3 : correct it (normalization) : 10.015 x 10 1 = 1.0015 x 10 2 Step4 : Four digits for significand 1.002 x 10 2

49. 240-334 By Wannarat Example Floating- point Addition 0.5 + (-0.4375) 0.5 = 1/2 = 1/2 1 = 0.1 x 2 0 = 1.00 x 2 -1 -0.4375 = -7/16 = -7/2 4 = - 0.0111 = -1.110 x 2 -2 step 1 : -0.111 x 2 -1 step 2 : 1.0x 2 -1 + (-0.111 x 2 -1 )=0.001 x 2 -1 step 3 : 1.0 x 2 -4 step 4 : 0.0625

50. 240-334 By Wannarat Multiplication Floating-point Study in Text Book by yourself.

51. 240-334 By Wannarat Next on Lecture 4