1. Multiplication & Division
COE 308

2. Multiplication Algorithm
852
x 456
School Age
Algorithm
6 x 852 x 100
5 x 852 x 101 +
4 x 852 x 102
Algorithm:
Compute Partial Products
Multiply Multiplicand by EACH DIGIT of Multiplier
Single Digit Multiplication
Multiply the product by the order of the digit (x 10i)
Multiplication by a power of the base (10i) is a Shift Left by i positions
Add Partial Products
Multiple Additions
COE 308

3. Multiplication in Binary x
1 x x 20
1 x x 21
0 x x 22
0 x x 23 +
1 x x 24
Because there are only two digits in binary (0 and 1). The multiplication algorithm becomes only:
Shift Multiplicand
Easy to Implement
Multiply Shifted Multiplicand by 1 or 0
A x 1 = A; A x 0 = 0
Add the Shifted Multiplicands
Addition of many operands?
Issue: How to add more than two operands
at the same time ?
COE 308

4. Adding Partial Products
Issue: How to add more than two operands at the same time ?
h (0 on 32 bits)
Multiplicand
Uses many Adders
Need circuit that uses one to few adders because of size limitations
Parallel Multipliers are used in high performance, multiplication intensive, architectures like DSP (Digital Signal Processing).
bits 1 2
Multiplier 30 31
TOO EXPENSIVE + 31 31 + 31 + 31 +
COE 308

5. Iterative Solution Full Parallel Multiplier is too expensive Solution
Iteratively add the partial products
Advantages
Inconvenients
Uses ONE
Adder Only
Much Slower than
Parallel Multiplication
Circuit
COE 308

6. First Multiplication Algorithm
Shift the Multiplicand Left to realize the multiplication by the order of the digit
Multiplicand
Shift the Multiplier right to get out each digit LSB first and MSB last
Shift Left
64 bits
Multiplier
Shift Right
32 bits
Add the product register content to every potential partial product (shifted multiplicand) all the time. Result is only written when appropriate
64-bit ALU
Control test
Product
Write
64 bits
Control the write of the product register to only add partial products corresponding to a multiplier digit equal to 1
COE 308

7. First Multiplication Algorithm(2)
Start
Bit 0 of
Multiplier = 0 ? =1 =0
Product  Product + Multiplicand
Shift Left Multiplicand with 1 bit
Shift Right Multiplier with 1 bit
32nd Repetition?
Yes: 32 repetitions
No: < 32 repetitions
Done
COE 308

8. Multiplication Circuit Improvement
Current Circuit has
64-bits Multiplier Register used to shift the Multiplier.
Shifting the Multiplier means inserting 0s (known value).
Reserving bits for holding known values is a waste of resources
Anytime, Register contains 32 data bits and 32 0s.
100% overhead just to shift
64-bits Adder is not necessary because:
Addition is done between two 32 bits operands
Either add lower bits of product with lower 0s of the shifted multiplier
Or add the higher bits of the product which are 0s with the leading bits of the shifted multiplicand
Need to Reduce the cost of the Multiplication Circuit
COE 308

9. Analogy Multiplication Method is the same.
Two Ways of Implementing the same algorithm
Shift the Multiplicand register forward and do not shift the Product register (what we have seen so far)
Shift the Product register backward and do not shift the Multiplicand register (the other method)
Similar to having two methods of making a moving scene in a movie
COE 308

10. Is The Car Moving Forward or the Trees moving Backward ???
Movie Making Tips
Is The Car Moving Forward
or the Trees moving Backward ???
COE 308

11. The Car is Moving Forward The Camera/Observer is attached to the car
Method 1
The Car is Moving Forward
The Camera/Observer is attached to the car
COE 308

12. Method 2 The Car is a Fake Car.
The Camera/Observer and the Fake Car are both fixed
The trees are pictures fixed on a moving panel
COE 308

13. Shifting Backwards Shift Multiplicand Left +
10011 x  +
10011 x
Product Initial
Product Initial
Mcand x 1 Shiftd 0 bits
Mcand x 1
Mcand x 1 Shiftd 1 bits
Sh. Product Right
Mcand x 1
Mcand x 0
Mcand x 0
Sh. Product Right
Mcand x 0
Mcand x 1 Shiftd 4 bits
Sh. Product Right
Mcand x 0
Multiplicand
Multiplier
Product
Sh. Product Right
Mcand x 1
Shift Multiplicand Left
No Shift for the Product
No Shift for the Multiplicand
Shift the Product Right (Backward)
COE 308

14. Second Multiply Algorithm
Multiplicand
32 bits
Multiplier
Shift Right
32-bit ALU
32 bits
Control test
Shift Right
Write
Product
64 bits
COE 308

15. Second Multiply Algorithm (2)
Start
Bit 0 of
Multiplier = 0 ? =1 =0
Product[63:32] 
Product[63:32] + Multiplicand
Shift Right Product with 1 bit
Shift Right Multiplier with 1 bit
32nd Repetition?
Yes: 32 repetitions
No: < 32 repetitions
Done
COE 308

16. Merge the lower 32-bits of Product Register with Multiplier Register
Another Improvement
In Second Multiplication Algorithm:
Initialize the 64-bit Product Register with 0s
Only the Upper 32-bits are added to the Multiplicand
The lower 32-bits 0s are shifted out as the Product register is shifted right
Merge the lower 32-bits of Product Register with Multiplier Register
COE 308

17. Third Multiply Algorithm
Multiplier Register merged with lower 32 bits of Product register
Multiplicand
32 bits
32-bit ALU
Control test
Shift Right
Write
Product
64 bits
COE 308

18. Third Multiply Algorithm (2)
Start
Bit 0 of
Product = 0 ? =1 =0
Product[63:32] 
Product[63:32] + Multiplicand
Shift Right Product with 1 bit
32nd Repetition?
Yes: 32 repetitions
No: < 32 repetitions
Done
COE 308

19. Signed Multiplication
Convert multiplier and multiplicand into positive numbers
Perform the multiplication
Compute the sign of the product
Apply the sign to the product by either complementing the product (<0) or leaving it as is (>0)
COE 308

20. Booth’s Algorithm
Principle: Minimization of Intermediate Additions by
Virtually reducing multiplier
Middle of run
End of run
Beginning of run
i+3
i+2
i+1 i
Normal Method: Product = Product + Mcand.(2i+3 + 2i+2 + 2i+1 + 2i)
Booth’s Method: Product = Product + Mcand (2i+4 -2i)
Current Bit
Bit to the right
Run
Operation 1
Beginning of a run of 1s
Subtract Multiplicand
Middle of a run of 1s
Do Nothing
End of a run of 1s
Add Multiplicand
Middle of run of 0s
Do nothing
COE 308

21. Multiplication in MIPS
Separate pair of 32 bits registers to contain the 64-bit product
Hi and Lo: 32 bits each. Result of multiplication instructions always in Hi:Lo
2 instructions to move the result from Hi/Lo to MIPS registers: mflo and mfhi
2 Multiply instructions
mult: signed multiplication
multu: unsigned multiplication
COE 308

22. Division 827 21 8 < 21 827 21 82 > 21 82 >= 21 x d 827 21
Select One digit from Dividend to compare to Divisor
827 21
8 < 21
Smaller than Divisor, Consider Two digits
827 21
82 > 21
Find biggest digit d (from 1 to 9) which satisfies:
82 >= 21 x d
82 > 21x1
82 > 21x2
82 > 21x3
82 < 21x 4
Use (4-1) = 3
Determine d using:
Intuition (Guessing) when performed by a Human
Algorithm that increases d until
Either d x 21 > 82; use (d-1)
Or d = 9
827 21
- 63
197 > 21x1
……………………
197 > 21x8
197 > 21x9
Use 9 39
197
- 189 8
COE 308

23. Division Algorithm (in Decimal)
Start
M >= Divisor No
Shift Left Next Digit of Dividend into M
Define M: temporary storage
Yes
d = 1
Define Q: Quotient
Q = 0
M <= d x Divisor No
d = 9 No
d = d + 1
M = Leftmost Digit of Dividend
Yes
Yes
d = d - 1
M = M – (d x Divisor)
Shift Left Next Digit of Dividend into M
Shift in d into Q
Done
No More
Digits in
Dividend No
Yes
M: Remainder
Q: Quotient
COE 308

24. Division in Binary
Many steps before finding a number > Divisor
Presence of leading 0s disturbs the conventional algorithm
Extract digits from Dividend and Shift them to align them with Divisor
In binary, d can only take the value 0 or 1.
Means:
Divisor x d <= Extracted Digits from Dividend
d = 1
Quotient Register: Shift Left Serial In from LSB
Every step the Extracted Digits are compared to the Divisor:
If Divisor x 1 > Extracted Digits  Shift in 0 in the Quotient
If Divisor x 1 <= Extracted Digits  Shift in 1 in the Quotient
Method of Extracting Digits from Dividend not Practical in Context of Logic Circuits
COE 308

25. Rest of the Algorithm Remains the Same
Forced Alignment
To Force the Alignment of the Dividend and the Divisor:
Multiply the Divisor by 2n (Shift Left by n), n being the number of bits of both the Dividend and the Divisor
Shift right (divide by 2) the Divisor until Divisor <= Dividend
< 0
>= 0
Rest of the Algorithm Remains the Same
COE 308

26. First Division Algorithm
Divisor
Shift right
64 bits
Quotient
Shift Left
64-bit ALU
32 bits
Control test
Remainder
Write
64 bits
COE 308

27. First Division Algorithm (2)
Start
Remainder 
Remainder - Divisor
Remainder ≥ 0
Test
Remainder
Remainder < 0
Shift Quotient to left
setting the new rightmost bit to 1
Restore original value of Remainder
Remainder  Remainder + Divisor
Shift Quotient to left
setting the new rightmost bit to 1
Shift Right Divisor with 1 bit
33rd Repetition?
Done
Yes: 33 repetitions
No: < 33 repetitions
COE 308

28. Division Algorithm Improvement
Current Circuit has
64-bits Divisor Register used to shift the Divisor.
Shifting the Divisor means inserting 0s (known value).
Reserving bits for holding known values is a waste of resources
Anytime, Register contains 32 data bits and 32 0s.
100% overhead just to shift
64-bits ALU is not necessary because:
Subtraction is done between two 32 bits operands (after alignment of Divisor and Dividend)
Need to Reduce the cost of the Division Circuit
COE 308

29. Shifting Dividend Forward
Shifting the Divisor Backward (Right) and Fixing the Dividend/Remainder
is equivalent to:
Fixing the Divisor and Shifting the Dividend/Remainder Forward (Left)
In Second Method:
Dividend/Remainder Register still 64-bits, initialized with Dividend aligned right with upper 32-bits initialized to 0
Divisor Register is reduced to 32-bits and is not shifted.
Similar to the Analogy made in improving the Multiplication Algorithm
COE 308

30. Second Division Algorithm
Divisor
32 bits
Quotient
Shift Left
32-bit ALU
32 bits
Control test
Shift Left
Remainder
Write
64 bits
COE 308

31. Merge the lower 32-bits of Remainder Register with Quotient Register
Another Improvement
In Second Algorithm:
Remainder Register upper 32-bits initialized to 0s
Remainder Register is shifted left 32 times.
0s are inserted in the LSB of the Remainder Register
Lower 32 bits end-up with 0s
Quotient Register: 32-bit LSB serial-in left shift register
Data is progressively shifted-in in the Quotient Register
Merge the lower 32-bits of Remainder Register
with Quotient Register
COE 308

32. Final Division Algorithm
Divisor
32 bits
32-bit ALU
Shift Right
Remainder
Write
Control test
Shift Left
64 bits
COE 308

33. Division in MIPS
Separate pair of 32 bits registers to contain the 64-bit remainder:
Hi and Lo: 32 bits each.
Lo: Contains Quotient
Hi: Contains Remainder
2 instructions to move the result from Hi/Lo to MIPS registers: mflo and mfhi
2 Divide instructions
div: signed division
divu: unsigned division
COE 308