1. EE204 L03-ALUHina Anwar Khan 20111 EE204 Computer Architecture Lecture 03- ALU

2. EE204 L03-ALU Hina Anwar Khan Spring 2011 2 Limits of Computer Numbers Bits can represent anything! Characters?  26 letter => 5 bits  upper/lower case + punctuation => 7 bits (in 8)  rest of the world’s languages => 16 bits (unicode) Logical values?  0 -> False, 1 => True colors ? locations / addresses? commands? but N bits => only 2 N things

3. EE204 L03-ALU Hina Anwar Khan Spring 2011 3 Arithmetic Operations Numbers represented in binary Positive & Negative numbers ? Largest Number ? Result larger than largest number? Fractions & real numbers representation? Hardware add, subtract, multiply, divide?

4. EE204 L03-ALU Hina Anwar Khan Spring 2011 4 Positive & Negative Numbers So far, unsigned numbers  Obvious solution: define leftmost bit to be sign!  Representation called sign and magnitude MIPS uses 32-bit integers. +1 ten would be: 0000 0000 0000 0000 0000 0000 0000 0001 And - 1 ten in sign and magnitude would be: 1000 0000 0000 0000 0000 0000 0000 0001 Arithmetic circuit more complicated  Special steps depending whether signs are the same or not

5. EE204 L03-ALU Hina Anwar Khan Spring 2011 5 2’s Complement Number line 2 N-1 non- negatives 2 N-1 negatives one zero how many positives? comparison? overflow? 00000 00001 00010 11111 11100 10000 01111 10001 0 1 2 -2 -15 -16 15............

6. EE204 L03-ALU Hina Anwar Khan Spring 2011 6 Two’s Complement Formula Can represent positive and negative numbers in terms of the bit value times a power of 2:  d 31 x -2 31 + d 30 x 2 30 +... + d 2 x 2 2 + d 1 x 2 1 + d 0 x 2 0 Example 1111 1111 1111 1111 1111 1111 1111 1100 two = 1x-2 31 +1x2 30 +1x2 29 +... +1x2 2 +0x2 1 +0x2 0 = -2 31 + 2 30 + 2 29 +... + 2 2 + 0 + 0 = -2,147,483,648 ten + 2,147,483,644 ten = -4 ten Note: need to specify width: we use 32 bits

7. EE204 L03-ALU Hina Anwar Khan Spring 2011 7 Sign extension Convert 2’s complement number using n bits to more than n bits Simply replicate the most significant bit (sign bit) of smaller to fill new bits  2’s comp. positive number has infinite 0s  2’s comp. negative number has infinite 1s  16-bit -4 ten to 32-bit: 1111 1111 1111 1100 two 1111 1111 1111 1111 1111 1111 1111 1100 two

8. EE204 L03-ALU Hina Anwar Khan Spring 2011 8 Signed v. Unsigned Comparisons X = 1111 1111 1111 1111 1111 1111 1111 1100 two Y = 0011 1011 1001 1010 1000 1010 0000 0000 two Is X > Y?  unsigned: YES  signed:NO Converting to decimal to check  Signed comparison: -4 ten < 1,000,000,000 ten?  Unsigned comparison: -4,294,967,292 ten < 1,000,000,000 ten?  slt, slti and sltu, sltiu instructions

9. EE204 L03-ALU Hina Anwar Khan Spring 2011 9 Numbers are stored at addresses Memory is a place to store bits A word is a fixed number of bits (eg, 32) at an address  also fixed no. of bits Addresses are naturally represented as unsigned numbers 101101100110 00000 11111 = 2 k - 1 01110

10. EE204 L03-ALU Hina Anwar Khan Spring 2011 10 Addition & Subtraction Addition:Binary Addition Subtraction:Binary 2’s comp. Addition Overflow  Adding two positive numbers  Adding two negative numbers add, addi, sub  Cause exception on overflow addu, addiu, subu  Cause no exception on overflow

11. EE204 L03-ALU Hina Anwar Khan Spring 2011 11 Determining Overflow 0111 (+7)0111 (+7) 0101 (+5)1011 (-5) 1100 (-4) 10010 (+2) 1001 (-7)1001 (-7) 0101 (+5) 1011 (-5) 1110 (-2) 10100 (+4) Overflow occurs when the signs of the values are the same, and the sign of the result is different. Overflow if Cin to MSB is different from Cout of MSB

12. EE204 L03-ALU Hina Anwar Khan Spring 2011 12 Arithmetic and Logic Unit The ALU is at the heart of the CPU  Does math and logic The ALU is primarily involved in R-type instructions  Perform an operation on two registers and produce a result Where is the operation specified?  The instruction type specifies the operation  The ALU will have to be controlled by the instruction opcode

13. EE204 L03-ALU Hina Anwar Khan Spring 2011 13 Arithmetic Logic Unit (ALU)

14. EE204 L03-ALU Hina Anwar Khan Spring 2011 14 ALU - Logic Operations 0 1 A B Operation Result 2-to-1 Mux If Operation = 0, Result = A B If Operation = 1, Result = A  B Start out by supporting AND and OR operations Two operands, two results. We need only one result... The Operation input comes from logic that looks at the opcode

15. EE204 L03-ALU Hina Anwar Khan Spring 2011 15 Arithmetic Unit ab cin 01 00 01 11 10

16. EE204 L03-ALU Hina Anwar Khan Spring 2011 16 Arithmetic Unit InputOutput ABCinSCout 00000 00110 01010 01101 10010 10101 11001 11111

17. EE204 L03-ALU Hina Anwar Khan Spring 2011 17 Adding to our ALU CarryIn CarryOut ALU A B C out C in Result C in C out Op (2 bits) OperationFunction 00A B 01A  B 10A + B OperationFunction 00A B 01A  B 10A + B + (Op is now 2 bits) Add an Adder Connect CarryIn (from previous bit) and CarryOut (to next bit) Expand Mux to 3-to-1 (Op is now 2 bits) 0 1 Operation Result A B 2 0 1

18. EE204 L03-ALU Hina Anwar Khan Spring 2011 18 1-bit & 32-bit ALU Connect to common Operation controls  Now we can do 32-bit AND and OR operations Stack 32 of our 1-bit ALU’s together  Each one gets one bit from A and one from B Connect C out ’s to C in ’s  Now, 32-bit adds will work  Note: Carry will ripple through the stages, one at a time Ripple-Carry Adder

19. EE204 L03-ALU Hina Anwar Khan Spring 2011 19 Subtracting 0 1 B 0 1 A Operation Result + 2 CarryIn CarryOut BInvert For subtraction: Set Carry In of LSB to 1, Set BInvert to 1 For subtraction: Set Carry In of LSB to 1, Set BInvert to 1 Add an inverter, and a signal BInvert to get B Now, how about that +1?  Carry In to LSB is unused (always zero)  Set it to 1! Subtraction just sets BInvert and C in to 1 B Our ALU can add now, but what about subtraction? To compute A - B, we can instead compute A + (-B) In 2’s complement, -B = B + 1 Set to 1 for LSB

20. EE204 L03-ALU Hina Anwar Khan Spring 2011 20 Subtraction a input b input Cin input output A00A 0B0B A01A+1 A0*0A – 1 AB1A+B+1 AB*1A – B AB0A + B AB*0A – B -1

21. EE204 L03-ALU Hina Anwar Khan Spring 2011 21 Support for SLT A<B is equivalent to (A - B) < 0 Subtract B from A  If the result is negative, then set LSB of Result to ‘1’, all others to ‘0’  The result is negative if the MSB after the subtraction is ‘1’ (Two’s complement) Result 0 1 A Operation + 2 B CarryIn CarryOut 0 1 BInvert Less We’re going to have to do something different for the MSB and the LSB We need to support the SLT operation  Set Result to 0000 0000 0000 0000 0000 0000 0000 0001 if A <B 0 1 2 3 Less will be ‘0’ for bits 1-31, special for bit 0

22. EE204 L03-ALU Hina Anwar Khan Spring 2011 22 That tricky MSB To properly execute the SLT, we need to Set the LSB if the MSB is ‘1’  (After a subtraction) OverFlow Set 0 1 A Operation Result + 2 B CarryIn CarryOut 0 1 BInvert 3 Less MSB Only Can’t use the ‘Result’ of the MSB  Op will set the Mux to the ‘Less’ Field  Bring out the adder output directly: ‘Set’ Also, we need to check for overflow  Overflow if C in to MSB is different from C out of MSB

23. EE204 L03-ALU Hina Anwar Khan Spring 2011 23 Supporting the SLT instruction

24. EE204 L03-ALU Hina Anwar Khan Spring 2011 24 Implementing slt instruction

25. EE204 L03-ALU Hina Anwar Khan Spring 2011 25 32-bit ALU with Zero detector

26. EE204 L03-ALU Hina Anwar Khan Spring 2011 26 ALU ALU controlFunction 000And 001Or 010Add 110Subtract 111Set on less than

27. EE204 L03-ALU Hina Anwar Khan Spring 2011 27 How fast can 32-bit ALU add? Carry propagates through the adders 64-bit adder slower than 32-bit adder Solution?  Look-Ahead Carry Generator

28. EE204 L03-ALU Hina Anwar Khan Spring 2011 28 Is a 32-bit ALU as fast as a 1-bit ALU? c 1 = b 0 c 0 + a 0 c 0 + a 0 b 0 c 2 = b 1 c 1 + a 1 c 1 + a 1 b 1 c 2 = c 3 = b 2 c 2 + a 2 c 2 + a 2 b 2 c 3 = c 4 = b 3 c 3 + a 3 c 3 + a 3 b 3 c 4 = Not feasible! Why? Problem: ripple carry adder is slow

29. EE204 L03-ALU Hina Anwar Khan Spring 2011 29 An approach in-between our two extremes Motivation:  If we didn't know the value of carry-in, what could we do?  When would we always generate a carry? g i = a i b i  When would we propagate the carry? p i = a i + b i Did we get rid of the ripple? c 1 = g 0 + p 0 c 0 c 2 = g 1 + p 1 c 1 c 2 = c 3 = g 2 + p 2 c 2 c 3 = c 4 = g 3 + p 3 c 3 c 4 = Feasible! Why? Carry-lookahead adder

30. EE204 L03-ALU Hina Anwar Khan Spring 2011 30 Use principle to build bigger adders Can’t build a 16 bit adder this way... (too big) Could use ripple carry of 4-bit CLA adders Better: use the CLA principle again!

31. EE204 L03-ALU Hina Anwar Khan Spring 2011 31 Carry Look-Ahead Generator

32. EE204 L03-ALU Hina Anwar Khan Spring 2011 32 1-bit Full Adder

33. EE204 L03-ALU Hina Anwar Khan Spring 2011 33 Carry Generate & Propagate where

34. EE204 L03-ALU Hina Anwar Khan Spring 2011 34 Look-Ahead Carry Generator