999999-1 XYZ 1/7/2016 MIT Lincoln Laboratory APS-2 Diode Simulation First Look V. Suntharalingam 27 July 2007.

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Presentation transcript:

XYZ 1/7/2016 MIT Lincoln Laboratory APS-2 Diode Simulation First Look V. Suntharalingam 27 July 2007

MIT Lincoln Laboratory XYZ 1/7/2016 APS2 Tier-1 Photodiode Layout Channel Stop (n) p+ Graded p+ 24  m 9  m 1.5  m 12  m Pixel Layout (Showing Implants only) Mask Layout View (Showing Metal Fill) Metal Fill Pixel with contacts leading to 3D Via Substrate is 3000 ohm-cm FZ n-type

MIT Lincoln Laboratory XYZ 1/7/2016 APS2 Tier-1 Pixel Array Layout 256 x 256 pixel array (p+ side of each diode connected to Tier-2 SOI circuit) Scupper Pixels Substrate Contact (n+) Ring

MIT Lincoln Laboratory XYZ 1/7/2016 Mask Layout – Tier-1 Diodes Partial View of Pixel Array Top Left Corner 256 x 256 pixel array 4-pixel-wide inner frame, tied together as Scupper Presently biased to VRST1=VRST2 4-pixel-wide outer frame, tied together for substrate (n+) contact Implant layer shown as yellow

MIT Lincoln Laboratory XYZ 1/7/2016 Two-Dimensional Simulation – Description Initial questions: –At what voltage is the silicon depleted? –What is the Electric field profile under the wide channel stops? Simulation Setup: –50-um thick silicon –5 x 24-um pixels –Simplified doping profile Process simulator (Athena) was run to obtain general values –Positive bias applied to substrate and all channel stops (n-CS regions common with substrate) –Photodiode nodes (p+) held at 0V –No photogeneration - these are “empty well” profiles Pixel #3 (p+) n-CS n-3000 ohm-cm (3e12) 50 um Depth n-substrate contact 5 x 24 um Width Caution: Aspect Ratio is severely distorted in these plots! Doping Profiles

MIT Lincoln Laboratory XYZ 1/7/2016 Two-Dimensional Simulation of 5 Pixels Potential Contours Show Effect of Varying Substrate Bias Vsub=0V Vsub=2VVsub=5V Vsub=10V Vsub=14V 0V 2V 5V 10V Vsub=14V Potential (V) Potential profile at center of pixel-3 (vertical “cut-line”) Depth into Si “cut-line” (filename error) For Vsub=10V, 15V: E-field is vertical from ~25 to 50 um depth into silicon. Nearer to the frontside we observe the lateral influence of the Channel Stops

MIT Lincoln Laboratory XYZ 1/7/2016 Electric Field Vectors & Potential Profile Center Pixel (#3) Center Pixel is isolated from simulation artifacts arising from left and right boundary conditions Vsub=10V (at backside) Vsub=15V (at backside) 10V 15V 0V Pixel #3 Vertical Field Transition at ~9um (Lowest Field in CS) 24 um 18

MIT Lincoln Laboratory XYZ 1/7/2016 Reverse Bias of 15V Similar to Previous Slide Vsub=15V (at backside) 15V 0V 8.5 um 18 Microns 0V

MIT Lincoln Laboratory XYZ 1/7/2016 Substrate Bias Influence on Vertical Profile 5V 10V Vsub=15V Potential (V) Depth into Si 50 Potential (V) Electric Field (V/cm) Depth into Si 5V 10V Vsub=15V Vertical Cut Through Pixel Center (p+) Vertical Cut Through Channel Stop We should try testing with 15V 5V 10V Vsub=15V Note direction of Field E E E

MIT Lincoln Laboratory XYZ 1/7/2016 Substrate Bias Influence on Horizontal Profile Depth = 9um Potential (V) Electric Field (V/cm) Pixel #3 5V 10V Vsub=15V Horizontal Cut Across Pixel #3 and y=9um Channel Stop 5V 10V Vsub=15V Pixel #3 Center #2#4 note scale